Water-cooled open RISC-V AI accelerator board, V1. CHARRUA v1.2 + AGPL v3.
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rtl: InterGemminiXbar v1 — N×N decoupled crossbar with round-robin arbitration (#115)
2026-05-26 20:39:51 -03:00
.forgejo/workflows fix(ci): fluidpop-runner + workflow node-compatibility (#12) 2026-05-24 05:20:54 -03:00
board feat(cfd): OpenFOAM cold-plate case template + sweep orchestrator (Issue #5) (#17) 2026-05-24 11:43:25 -03:00
docs docs(benchmarks): add baseline-gemmini-rocket skeleton for Phase 2 (#101) 2026-05-26 09:20:48 -03:00
formal Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00
infra feat(agents): spec-designer role — promote Stub SPECs to Draft via claude (#80) 2026-05-26 00:54:45 -03:00
phy Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00
rtl rtl: InterGemminiXbar v1 — N×N decoupled crossbar with round-robin arbitration (#115) 2026-05-26 20:39:51 -03:00
sim Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00
sw sw/runtime: scaffold §14.3 canonical names + tree README (#103) 2026-05-26 09:17:02 -03:00
synth Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00
.gitignore rtl: PCIeHostBridge skeleton + chiseltest elaborate bench (#65) 2026-05-25 17:18:32 -03:00
CHANGELOG.md Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00
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README.md Initial commit: PLAN.md v0.6, repo skeleton, Phase 1 deliverables 2026-05-24 03:20:41 -03:00

FluidPopV1

Placa aceleradora de IA open-source com 8 SoCs RISC-V customizados, refrigeração líquida obrigatória, projeto de soberania digital latino-americana.

Open-source 8-die RISC-V AI accelerator board, water-cooled, sovereign-by-design.


Visão geral (PT-BR)

FluidPopV1 é a primeira geração de uma família de placas aceleradoras de IA projetadas pela PopSolutions Cooperativa de Tecnologia (Barueri, SP). O projeto integra:

  • 8 SoCs RISC-V com aceleradores matriciais Gemmini customizados, conectados por um interconect proprietário aberto chamado PopLink (topologia toroidal 2x4).
  • 8 canais DDR5, um DIMM por SoC, modelo de memória não-coerente entre chips (orquestração explícita pelo runtime).
  • Refrigeração líquida obrigatória com cold plate único de cobre OFC, microcanais paralelos sob cada chip, ports G1/4" quick-disconnect.
  • Form factor OAM 2.0 compatível com servidores OCP.
  • Stack de software AGPL v3, hardware/RTL CHARRUA v1.2.

Duas configurações compartilham o mesmo Chisel codebase parametrizado:

Tier Process TOPS @ board Status
Edu IHP130 130 nm BiCMOS (open PDK) ~16 TOPS INT8 Phase 1-6 (proof of concept totalmente soberano, fab open)
Pro SMIC N+2 ~7 nm ~800 TOPS INT8 / ~1600 TOPS INT4 Phase 7+ (produção, design-soberano)

O plano completo está em PLAN.md, incluindo análise de falhas (Section 0), arquitetura do board e do chip (Sections 1-3), estrutura do repositório (Section 4), fases de execução (Sections 6-11), metodologia de verificação (Section 12), survey de PHY (Section 13), runtime multi-chip (Section 14), supply chain consciente de sanções (Section 15) e questões em aberto (Section 19).

Overview (EN)

FluidPopV1 is the first generation of an AI accelerator board family designed by PopSolutions Cooperativa de Tecnologia (Barueri, SP, Brazil). The board integrates 8 custom RISC-V SoCs with Gemmini matrix accelerators, connected by an open inter-chip interconnect named PopLink (2x4 torus topology), with mandatory water cooling.

Same Chisel codebase parameterizes two configurations: Edu (IHP130 open PDK, ~16 TOPS) and Pro (SMIC N+2, ~800-1600 TOPS).

See PLAN.md for the full specification.

Repository structure

fluidpop-v1/
├── PLAN.md                 # canonical plan (Sections 0-19)
├── README.md               # this file
├── LICENSE.md              # CHARRUA v1.2 (HW) + AGPL v3 (SW)
├── CHANGELOG.md
├── docs/                   # architecture, ADRs, specs, checkpoints, funding, supply chain, PHY
├── rtl/                    # Chisel RTL, PopLink stack, tests
├── sim/                    # Verilator + Spike + Cocotb
├── synth/                  # Sky130 / IHP130 synthesis flows
├── sw/                     # driver, runtime, compiler, frameworks
├── board/                  # PCB, cold plate, CFD, BMC, mech
├── phy/                    # PHY survey, spec, academic partnerships
├── formal/                 # Yosys-SBY proofs
├── .forgejo/workflows/     # CI pipelines
└── infra/forgejo/          # provision.sh (idempotent bootstrap)

Licenses

  • Hardware / RTL (CHARRUA v1.2) — modules under rtl/src/pop/, board files under board/, mechanical and PCB artifacts, ADRs.
  • Software (AGPL v3) — modules under sw/, infra/, sim/ orchestration, CI workflows, runtime headers.
  • Docs (CC BY-SA 4.0)README.md, PLAN.md, funding docs, checkpoints, supplier evaluations.
  • Upstream third-party (BSD-3-Clause) — Chipyard, Gemmini, rocket-chip.

See LICENSE.md for full breakdown.

Status

Phase 1 in progress. Weekly checkpoints committed to docs/checkpoints/YYYY-WW.md. Architecture decisions live as ADRs under docs/decisions/. Open issues track work on git.pop.coop/Fluid/fluidpop-v1/issues.

Contributing

Workflow is GitOps-first:

  1. Open an issue describing the change.
  2. Create a feature/<slug> branch from main.
  3. Push commits; CI runs sbt compile, scalafmt, and (on PR) full chiseltest unit suite.
  4. Open a pull request linked to the issue. CI green is a hard precondition for merge.
  5. After review and CI green, PR is merged (squash preferred).

Code, comments, ADRs, and commit messages in English. README user-facing sections, PACID proposals, and BR/LATAM-facing documents in Portuguese.

Contact