Fluid/fluidpop-v1

Fork 0

Add docs/spec/pop-soc-v1.md full chip spec skeleton #110

New issue

Open

opened 2026-05-26 15:05:10 -03:00 by navigator · 3 comments

navigator commented

2026-05-26 15:05:10 -03:00

Owner

Goal

Create the full chip spec skeleton at docs/spec/pop-soc-v1.md, listed as deliverable #1 in PLAN.md Section 10. The spec gathers chip-level architectural decisions (ADR-001 through ADR-007 plus ADR-012/014 from board context) into a contributor-facing canonical document so RTL, synthesis, and supply-chain work share a single chip reference.

Sections to include:

Overview (FluidPopSoC, master vs slave variants per Section 8.2 PopSoCConfig)
Compute resources (4 Gemminis per ADR-001, 16x16 systolic per ADR-002, 2 Rocket cores per ADR-006)
On-chip interconnect (4x4 intra-chip xbar per ADR-003, RoCC routing via PopRoCCRouter)
Memory hierarchy (256 KiB scratchpad per ADR-004, 1x DDR5 per chip with DRAMSim3 model per ADR-005)
Inter-chip interface (PopLink fabric ports per ADR-009; reference to poplink-phy-if.md)
Host interface (PCIe Gen4 x16 master-only via PCIeHostBridge; slaves have no host link)
Process / synth target (Sky130 vs IHP130 per ADR-007)
Power envelope (50 W typ / 70 W max per ADR-012)
Pin / package budget (~1100 BGA balls per ADR-014)
Open questions (clock domains, CSR map, reset topology — defer to ADRs)

Acceptance criteria

docs/spec/pop-soc-v1.md exists with the sections above
Status: Draft skeleton + Owner: TBD header
Each section has TODO markers and 2-3 line intent description
References ADR placeholder numbers (ADR-001..007, 009, 012, 014) explicitly
No fabricated frequencies, die sizes, or area numbers — only ranges/values already in PLAN.md
Cross-references PLAN.md Sections 10 and 8.1/8.2

Plan refs

Section 10 (deliverable #1), Section 8.1 (chip-level ADRs), Section 8.2 (custom modules), Section 13.3 (PHY interface decoupling)

Notes

Skeleton only — final architectural numbers move from Draft to Accepted via the per-ADR PRs. Avoid committing to specific frequencies or die area; this doc's job is structure plus a clear inventory of where each decision lives.

## Goal Create the full chip spec skeleton at `docs/spec/pop-soc-v1.md`, listed as deliverable #1 in PLAN.md Section 10. The spec gathers chip-level architectural decisions (ADR-001 through ADR-007 plus ADR-012/014 from board context) into a contributor-facing canonical document so RTL, synthesis, and supply-chain work share a single chip reference. Sections to include: - Overview (FluidPopSoC, master vs slave variants per Section 8.2 PopSoCConfig) - Compute resources (4 Gemminis per ADR-001, 16x16 systolic per ADR-002, 2 Rocket cores per ADR-006) - On-chip interconnect (4x4 intra-chip xbar per ADR-003, RoCC routing via PopRoCCRouter) - Memory hierarchy (256 KiB scratchpad per ADR-004, 1x DDR5 per chip with DRAMSim3 model per ADR-005) - Inter-chip interface (PopLink fabric ports per ADR-009; reference to `poplink-phy-if.md`) - Host interface (PCIe Gen4 x16 master-only via PCIeHostBridge; slaves have no host link) - Process / synth target (Sky130 vs IHP130 per ADR-007) - Power envelope (50 W typ / 70 W max per ADR-012) - Pin / package budget (~1100 BGA balls per ADR-014) - Open questions (clock domains, CSR map, reset topology — defer to ADRs) ## Acceptance criteria - [ ] `docs/spec/pop-soc-v1.md` exists with the sections above - [ ] `Status: Draft skeleton` + `Owner: TBD` header - [ ] Each section has `TODO` markers and 2-3 line intent description - [ ] References ADR placeholder numbers (ADR-001..007, 009, 012, 014) explicitly - [ ] No fabricated frequencies, die sizes, or area numbers — only ranges/values already in PLAN.md - [ ] Cross-references PLAN.md Sections 10 and 8.1/8.2 ## Plan refs Section 10 (deliverable #1), Section 8.1 (chip-level ADRs), Section 8.2 (custom modules), Section 13.3 (PHY interface decoupling) ## Notes Skeleton only — final architectural numbers move from Draft to Accepted via the per-ADR PRs. Avoid committing to specific frequencies or die area; this doc's job is structure plus a clear inventory of where each decision lives.

navigator added the

docs

agent:in-progress

labels

2026-05-26 15:05:10 -03:00

navigator commented

2026-05-26 15:06:09 -03:00

Author

Owner

No description provided.

navigator commented

2026-05-26 15:07:07 -03:00

Author

Owner

Deliverable is already on main — docs/spec/pop-soc-v1.md was rewritten as the Draft skeleton in PR #89 (commit b3521ad, merged 2026-05-26T01:11:12-03:00), roughly 14 h before this issue was opened (2026-05-26T15:05:10-03:00).

The current file satisfies every acceptance criterion in this issue:

All 10 sections present (Overview, Compute, Interconnect, Memory, PopLink, Host, Synth target, Power, Pin/package, Open questions).
Header has Status: Draft skeleton and Owner: TBD (lines 6–7).
Each section ends with a TODO marker plus 2–3 line intent.
ADR-001..007, 009, 012, 014 all explicitly referenced (header line 9, body bullets, References section).
No fabricated frequencies / die sizes / area numbers — only PLAN.md-derived ranges (e.g. ~45 GB/s DDR5-5600 per §2.3, 50 W / 70 W envelope per ADR-012, ~1100 BGA balls per ADR-014).
PLAN.md §10 and §8.1 / §8.2 cross-referenced in the header (line 8) and in §References.

Recommend: close this issue as a duplicate of #89 (or, if a follow-up scope was intended that is not visible in the body, re-file with the delta over what is already on main).

Deliverable is already on `main` — `docs/spec/pop-soc-v1.md` was rewritten as the Draft skeleton in **PR #89** (commit `b3521ad`, merged 2026-05-26T01:11:12-03:00), roughly 14 h before this issue was opened (2026-05-26T15:05:10-03:00). The current file satisfies every acceptance criterion in this issue: - All 10 sections present (Overview, Compute, Interconnect, Memory, PopLink, Host, Synth target, Power, Pin/package, Open questions). - Header has `Status: Draft skeleton` and `Owner: TBD` (lines 6–7). - Each section ends with a `TODO` marker plus 2–3 line intent. - ADR-001..007, 009, 012, 014 all explicitly referenced (header line 9, body bullets, References section). - No fabricated frequencies / die sizes / area numbers — only PLAN.md-derived ranges (e.g. ~45 GB/s DDR5-5600 per §2.3, 50 W / 70 W envelope per ADR-012, ~1100 BGA balls per ADR-014). - PLAN.md §10 and §8.1 / §8.2 cross-referenced in the header (line 8) and in §References. Recommend: close this issue as a duplicate of #89 (or, if a follow-up scope was intended that is not visible in the body, re-file with the delta over what is already on `main`).

navigator added

agent:blocked-resolver

and removed

agent:in-progress

labels

2026-05-26 15:12:13 -03:00

navigator commented

2026-05-26 15:12:13 -03:00

Author

Owner

No description provided.

No milestone

No project

No assignees

1 participant

Notifications

Due date

The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference

Fluid/fluidpop-v1#110

No description provided.

Rows
Columns