rtl: implement Chisel skeleton for InterChipFabric #53

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opened 2026-05-25 14:35:05 -03:00 by navigator · 2 comments

navigator commented

2026-05-25 14:35:05 -03:00

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Goal

Implement the Chisel skeleton for InterChipFabric per rtl/src/pop/specs/InterChipFabric.SPEC.md. This issue closes the gap between the SPEC text and a buildable Scala module, with an IO bundle, internal stubs, and a chiseltest unit testbench skeleton — no full behaviour yet.

Module dep status: depends on PopLinkPHY_Behavioral.

Acceptance criteria

rtl/src/pop/InterChipFabric.scala exists, compiles under Chipyard 1.13.0 with sbt compile green
IO bundle reflects the Interface section of InterChipFabric.SPEC.md (use ??? / DontCare for fields where the spec is TBD — annotate each with a // TBD per SPEC §<section> comment)
Module is wired into the parent (only for non-leaf modules; leaves can stand alone)
rtl/tests/InterChipFabric/InterChipFabricSpec.scala exists with a chiseltest AnyFlatSpec skeleton: at least one test that elaborates the module via should "elaborate"
Header preserved: SPDX-License-Identifier: CHARRUA-1.2 on the Scala source; AGPL-3.0-or-later on the test
No fabricated values for spec TBD items — leave as DontCare with comment, do not invent widths/timing

Blocked on

#46 (Chipyard install) — without the toolchain, sbt compile cannot run.

Plan refs

PLAN.md §8.2 (custom module list); §12.3 (per-module verification floor). ADRs that constrain this module: see SPEC file header.

Notes

Coverage targets and full behaviour come in follow-up issues. This issue is the skeleton + elaborate.
Do not modify the SPEC file itself in this PR — SPEC edits are separate decisions.

## Goal Implement the Chisel skeleton for `InterChipFabric` per `rtl/src/pop/specs/InterChipFabric.SPEC.md`. This issue closes the gap between the SPEC text and a buildable Scala module, with an IO bundle, internal stubs, and a chiseltest unit testbench skeleton — no full behaviour yet. **Module dep status:** depends on PopLinkPHY_Behavioral. ## Acceptance criteria - [ ] `rtl/src/pop/InterChipFabric.scala` exists, compiles under Chipyard 1.13.0 with `sbt compile` green - [ ] IO bundle reflects the **Interface** section of `InterChipFabric.SPEC.md` (use `???` / `DontCare` for fields where the spec is `TBD` — annotate each with a `// TBD per SPEC §<section>` comment) - [ ] Module is wired into the parent (only for non-leaf modules; leaves can stand alone) - [ ] `rtl/tests/InterChipFabric/InterChipFabricSpec.scala` exists with a chiseltest `AnyFlatSpec` skeleton: at least one test that elaborates the module via `should "elaborate"` - [ ] Header preserved: `SPDX-License-Identifier: CHARRUA-1.2` on the Scala source; `AGPL-3.0-or-later` on the test - [ ] No fabricated values for spec `TBD` items — leave as `DontCare` with comment, do not invent widths/timing ## Blocked on - #46 (Chipyard install) — without the toolchain, `sbt compile` cannot run. ## Plan refs PLAN.md §8.2 (custom module list); §12.3 (per-module verification floor). ADRs that constrain this module: see SPEC file header. ## Notes - Coverage targets and full behaviour come in follow-up issues. This issue is the **skeleton + elaborate**. - Do **not** modify the SPEC file itself in this PR — SPEC edits are separate decisions.