rtl(InterGemminiXbar): chisel skeleton + chiseltest elaborate-only spec #64

Merged

navigator merged 1 commit from auto/issue-49-20260525T200104Z_issue49 into main

2026-05-25 17:10:06 -03:00

navigator commented

2026-05-25 17:08:47 -03:00

Owner

Closes #49.

What

Skeleton for InterGemminiXbar (ADR-003 4×4 intra-chip crossbar). Satisfies PLAN.md §12.3 step 1 (module elaborates) and step 2 (chiseltest harness exists) without touching the still-stub SPEC.

rtl/src/pop/InterGemminiXbar.scala — package chipyard.pop, empty IO bundle, every SPEC §Interface facet (ingress/egress decoupled ports, address-range routing table, per-port back-pressure) annotated // TBD per SPEC §<section>. SPDX-License-Identifier: CHARRUA-1.2.
rtl/tests/InterGemminiXbar/InterGemminiXbarSpec.scala — AnyFlatSpec + ChiselScalatestTester with a single should "elaborate" test. SPDX-License-Identifier: AGPL-3.0-or-later.

Why

The SPEC at rtl/src/pop/specs/InterGemminiXbar.SPEC.md is still Stub — every Interface / Behavior / Invariants field is TBD. Per issue #49 acceptance criteria the skeleton must elaborate without fabricating widths, port counts or timing. The IO bundle is therefore empty, with TBD comments pointing back at each SPEC section. Concrete ports, behaviour, golden model and coverage land in follow-up issues once the SPEC is promoted.

Leaf module per issue — no parent wiring this PR.

Verification

Dropped both files into ~/chipyard/generators/chipyard/src/{main,test}/scala/pop/ and ran against Chipyard 1.13.0 (commit 69eba86, sbt 1.12.11):

sbt 'project chipyard' compile — green (56 s)
sbt 'project chipyard' Test/compile — green (55 s, the InterGemminiXbarSpec file among the 2 sources compiled)

Temp copies were removed. No build.sbt is introduced in this repo; CI's sbt-compile job remains in its current "skipped until build.sbt lands" state (see .forgejo/workflows/build.yml).

Mirrors the resolution of #48 / PR #63 (PopRoCCRouter skeleton).

ADR / Plan refs

PLAN.md §8.2 (custom module list)
PLAN.md §12.3 (per-module verification floor)
ADR-003 (4×4 intra-chip crossbar)
SPEC at rtl/src/pop/specs/InterGemminiXbar.SPEC.md (left untouched)

Out of scope

Lifting SPEC from Stub
Any Bundle field with a concrete width, port count or flit layout
Functional tests, golden model, coverage report

Closes #49. ## What Skeleton for `InterGemminiXbar` (ADR-003 4×4 intra-chip crossbar). Satisfies PLAN.md §12.3 step 1 (module elaborates) and step 2 (chiseltest harness exists) without touching the still-stub SPEC. - `rtl/src/pop/InterGemminiXbar.scala` — `package chipyard.pop`, empty IO bundle, every SPEC §Interface facet (ingress/egress decoupled ports, address-range routing table, per-port back-pressure) annotated `// TBD per SPEC §<section>`. `SPDX-License-Identifier: CHARRUA-1.2`. - `rtl/tests/InterGemminiXbar/InterGemminiXbarSpec.scala` — `AnyFlatSpec` + `ChiselScalatestTester` with a single `should "elaborate"` test. `SPDX-License-Identifier: AGPL-3.0-or-later`. ## Why The SPEC at `rtl/src/pop/specs/InterGemminiXbar.SPEC.md` is still **Stub** — every Interface / Behavior / Invariants field is `TBD`. Per issue #49 acceptance criteria the skeleton must elaborate without fabricating widths, port counts or timing. The IO bundle is therefore empty, with TBD comments pointing back at each SPEC section. Concrete ports, behaviour, golden model and coverage land in follow-up issues once the SPEC is promoted. Leaf module per issue — no parent wiring this PR. ## Verification Dropped both files into `~/chipyard/generators/chipyard/src/{main,test}/scala/pop/` and ran against Chipyard 1.13.0 (commit `69eba86`, sbt 1.12.11): - `sbt 'project chipyard' compile` — green (56 s) - `sbt 'project chipyard' Test/compile` — green (55 s, the `InterGemminiXbarSpec` file among the 2 sources compiled) Temp copies were removed. No `build.sbt` is introduced in this repo; CI's sbt-compile job remains in its current "skipped until build.sbt lands" state (see `.forgejo/workflows/build.yml`). Mirrors the resolution of #48 / PR #63 (PopRoCCRouter skeleton). ## ADR / Plan refs - PLAN.md §8.2 (custom module list) - PLAN.md §12.3 (per-module verification floor) - ADR-003 (4×4 intra-chip crossbar) - SPEC at `rtl/src/pop/specs/InterGemminiXbar.SPEC.md` (left untouched) ## Out of scope - Lifting SPEC from Stub - Any Bundle field with a concrete width, port count or flit layout - Functional tests, golden model, coverage report

navigator added 1 commit

2026-05-25 17:08:47 -03:00

rtl(InterGemminiXbar): chisel skeleton + chiseltest elaborate-only spec

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b3ca91521e

Closes #49.

Adds the scaffold required by PLAN.md §12.3 step 1 (module elaborates)
and step 2 (chiseltest harness exists) so follow-up issues can layer
behaviour, golden model and coverage without lifting the SPEC out of
stub state.

- rtl/src/pop/InterGemminiXbar.scala: package chipyard.pop, empty IO
  bundle with each SPEC §Interface facet (ingress/egress decoupled
  ports, address-range routing table, per-port back-pressure)
  annotated `// TBD per SPEC §<section>`. SPDX CHARRUA-1.2.
- rtl/tests/InterGemminiXbar/InterGemminiXbarSpec.scala: AnyFlatSpec +
  ChiselScalatestTester with a single `should "elaborate"` test.
  SPDX AGPL-3.0-or-later.

Verified by dropping both files into
~/chipyard/generators/chipyard/src/{main,test}/scala/pop/ and running
against Chipyard 1.13.0 (commit 69eba86, sbt 1.12.11):

- sbt 'project chipyard' compile     -> success (56 s)
- sbt 'project chipyard' Test/compile -> success (55 s)

Mirrors the resolution of #48 / PR #63 (PopRoCCRouter skeleton). No
build.sbt is introduced; CI's sbt-compile lane remains
skipped-until-build.sbt-lands per .forgejo/workflows/build.yml. SPEC
stays Stub — its promotion is a separate decision.