Draft docs/spec/pop-soc-v1.md full chip spec skeleton #84

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opened 2026-05-26 00:55:58 -03:00 by navigator · 2 comments

navigator commented

2026-05-26 00:55:58 -03:00

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Goal

Create the full chip spec skeleton at docs/spec/pop-soc-v1.md, listed as deliverable #1 in PLAN.md Section 10. The spec gathers chip-level architectural decisions (ADR-001 through ADR-007) into a single contributor-facing document so RTL, synthesis, and supply-chain work share a canonical chip reference.

Sections to include:

Overview (FluidPopSoC, master vs slave variants per Section 8.2 PopSoCConfig)
Compute resources (4 Gemminis per ADR-001, 16x16 systolic per ADR-002, 2 Rocket cores per ADR-006)
On-chip interconnect (4x4 intra-chip xbar per ADR-003, RoCC routing via PopRoCCRouter)
Memory hierarchy (256 KiB scratchpad per ADR-004, 1x DDR5 per chip with DRAMSim3 model per ADR-005)
Inter-chip interface (PopLink fabric ports per ADR-009; PHY interface reference to poplink-phy-if.md)
Host interface (PCIe Gen4 x16 master-only via PCIeHostBridge, slaves have no host link)
Process / synth target (Sky130 vs IHP130 per ADR-007)
Power envelope (50 W typ / 70 W max per ADR-012)
Pin / package budget (~1100 BGA balls per ADR-014)
Open questions (clock domains, CSR map, reset topology — defer to ADRs)

Acceptance criteria

docs/spec/pop-soc-v1.md exists with the sections above
Status: Draft skeleton + Owner: TBD header
Each section has TODO markers and 2-3 line intent description
References the relevant ADR placeholder numbers (ADR-001..007, 009, 012, 014) explicitly
No fabricated frequencies, die sizes, or area numbers — only ranges/values already in PLAN.md
Cross-references PLAN.md Sections 10 and 8.1/8.2

Plan refs

Section 10 (deliverable #1), Section 8.1 (chip-level ADRs), Section 8.2 (custom modules), Section 13.3 (PHY interface decoupling)

Notes

Skeleton only — final architectural numbers come from ADRs as they move from Draft to Accepted. Avoid committing to specific frequencies or die area; the doc's job is structure plus a clear inventory of where each decision lives.

## Goal Create the full chip spec skeleton at `docs/spec/pop-soc-v1.md`, listed as deliverable #1 in PLAN.md Section 10. The spec gathers chip-level architectural decisions (ADR-001 through ADR-007) into a single contributor-facing document so RTL, synthesis, and supply-chain work share a canonical chip reference. Sections to include: - Overview (FluidPopSoC, master vs slave variants per Section 8.2 PopSoCConfig) - Compute resources (4 Gemminis per ADR-001, 16x16 systolic per ADR-002, 2 Rocket cores per ADR-006) - On-chip interconnect (4x4 intra-chip xbar per ADR-003, RoCC routing via PopRoCCRouter) - Memory hierarchy (256 KiB scratchpad per ADR-004, 1x DDR5 per chip with DRAMSim3 model per ADR-005) - Inter-chip interface (PopLink fabric ports per ADR-009; PHY interface reference to poplink-phy-if.md) - Host interface (PCIe Gen4 x16 master-only via PCIeHostBridge, slaves have no host link) - Process / synth target (Sky130 vs IHP130 per ADR-007) - Power envelope (50 W typ / 70 W max per ADR-012) - Pin / package budget (~1100 BGA balls per ADR-014) - Open questions (clock domains, CSR map, reset topology — defer to ADRs) ## Acceptance criteria - [ ] `docs/spec/pop-soc-v1.md` exists with the sections above - [ ] `Status: Draft skeleton` + `Owner: TBD` header - [ ] Each section has `TODO` markers and 2-3 line intent description - [ ] References the relevant ADR placeholder numbers (ADR-001..007, 009, 012, 014) explicitly - [ ] No fabricated frequencies, die sizes, or area numbers — only ranges/values already in PLAN.md - [ ] Cross-references PLAN.md Sections 10 and 8.1/8.2 ## Plan refs Section 10 (deliverable #1), Section 8.1 (chip-level ADRs), Section 8.2 (custom modules), Section 13.3 (PHY interface decoupling) ## Notes Skeleton only — final architectural numbers come from ADRs as they move from Draft to Accepted. Avoid committing to specific frequencies or die area; the doc's job is structure plus a clear inventory of where each decision lives.