- SystemVerilog 44.8%
- Python 41.8%
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PR #11 declared `clk_p`/`clk_n` as unconditionally `output` on the single `intercard_link` module. Per docs/hw/intercard-connector-pinout.md §2.1 §6, the forwarded source-synchronous clock is driven by the upstream card and consumed by the downstream card — so the original single-module surface only modeled the upstream role. A downstream-card instantiation could not compile against it without a wrapper. Apply Option C from issue #13 (least disruptive): - git-rename src/intercard_link.sv → src/intercard_link_upstream.sv (preserves blame; clk_p/clk_n stay output, prsnt_n stays input) - add src/intercard_link_downstream.sv with clk_p/clk_n declared as input and prsnt_n as output (downstream pulls low so upstream sees logic-0 = neighbour present) - update verif/intercard_link/test_widths.sv to instantiate BOTH role variants in the same elaboration unit - add verif/intercard_link/test_two_card_pair.sv: cross-wires upstream → downstream over the connector signal names. Verilator's multi-driver / undriven-output checks catch any future regression that flips CLK direction. Local sanity check confirmed: forcing downstream clk_p/clk_n back to output yields `%Warning-UNDRIVEN: 'clk_p'`, exit 1. - run_lint.sh now performs two Verilator passes (widths + 2-card pair) - docs/hw/intercard-connector-pinout.md §2.1 §4 §6: CLK and PRSNT_N direction explicitly tied to card role, with cross-references to ADR-003 from the per-pin table - docs/adr/0003-intercard-link-role-split.md: rationale, alternatives A/B/C/no-op, consequences, and a downstream-caller table Verilator 5.048 evidence (local): $ bash verif/intercard_link/run_lint.sh [run_lint] verilator Verilator 5.048 2026-04-26 rev v5.048 [run_lint] (1/2) widths: ...test_widths.sv → exit 0 [run_lint] (2/2) two-card pair: ...two_card_pair.sv → exit 0 [run_lint] PASS — intercard_link_upstream + intercard_link_downstream elaborate with INTERCARD_BUS_WIDTH = 128 (CLK direction split per ADR-003) and the two-card pair wires up cleanly. closes #13 refs #11, #14 Authored by Agent 2 (FPGA Hardware). Signed-off-by: Marcos <m@pop.coop> Co-authored-by: Marcos <m@pop.coop> |
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InnerJib7EA — POPC_16A
First Sail of the PopSolutions fleet. The validation tape-out.
InnerJib7EA is the first silicon product of PopSolutions Sails. SKU POPC_16A — embedded entry single-board RISC-V accelerator with 16 GB DDR5, targeting edge AI inference and on-device fine-tuning.
This is a deliberately small first silicon: monolithic die in Skywater 130nm via Google Open MPW shuttle, low cost, low risk. The goal is to validate the end-to-end design flow with the smallest possible blast radius.
Status
Sprint C (inner_jib_top.sv end-to-end integration) landed. A real
RISC-V program (mast/examples/direct/sum_ints.asm) now runs through:
upstream core.sv -> core_axi4_adapter -> axi4_master_simple -> axi4_mem_model
The cocotb test pre-populates instruction memory through the mem model's
loader back-door (added in MAST#8),
sets the core's PC, and asserts ena. The core then fetches instructions,
executes the loop, and emits the expected output sequence [0, 5, 4, 3, 2, 1, 0, 15] before halting.
This is the first program of any kind running on PopSolutions silicon- equivalent hardware in simulation. Every subsequent program (factorial, primes, matrix multiply, eventually GGML kernels) lands on the same path.
See docs/adr/0001-spec.md for the locked POPC_16A
specification.
Quick spec
| Parameter | Target |
|---|---|
| Process | Skywater 130nm (Open MPW) |
| Compute | 1 Compute Unit, RVA23 + RVV 1.0 + Xpop_matmul |
| DRAM | 16 GB DDR5-4800 SO-DIMM (single channel) |
| Host | PCIe Gen4 x4 (via LitePCIe) |
| TDP | < 25 W |
| Form factor | M.2 22110 NGFF accelerator card |
| Reference workload | GGML int4 inference of TinyLlama-1.1B |
| BOM target | R$ 800–1500 |
Run the testbench locally
One-time setup:
git clone --recursive git@git.pop.coop:pop/InnerJib7EA.git
cd InnerJib7EA
~/.pyenv/versions/3.12.10/bin/python3 -m venv mast/verif/.venv
source mast/verif/.venv/bin/activate
pip install cocotb cocotb-bus pytest
deactivate
ln -s ../mast/verif/.venv verif/.venv
Run:
source verif/.venv/bin/activate
cd verif/inner_jib_top
make
Expected output ends with:
** TESTS=2 PASS=2 FAIL=0 SKIP=0 **
Relationship to MAST
InnerJib7EA vendors popsolutions/MAST
as a git submodule under mast/. MAST holds the shared IP (RISC-V core,
compute unit, AXI4 subsystem, verification harness). This repo holds only
product-specific integration: top-level Verilog (src/inner_jib_top.sv),
spec ADRs, eventually PCB design files, datasheets, product tests.
When InnerJib7EA tape-outs to silicon, the MAST submodule pin is frozen at the specific MAST release used. That pin is the reproducibility contract.
License
Same dual-license model as MAST. See
mast/NOTICE.md.
Contributing
See mast/CONTRIBUTING.md
and the cooperative-affiliate-only policy in
mast/GOVERNANCE.md.
DCO sign-off required on every commit (git commit -s).