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Add docs/spec/poplink-phy-if.md PHY interface spec skeleton #109

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opened 2026-05-26 15:05:09 -03:00 by navigator · 3 comments

navigator commented

2026-05-26 15:05:09 -03:00

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Goal

Create the PopLink PHY interface spec skeleton at docs/spec/poplink-phy-if.md, named explicitly as Phase 1 PHY deliverable #2 in PLAN.md Section 13.4. The spec describes the PopLinkPHYIO Chisel bundle contract that decouples upper-layer fabric logic from the analog PHY implementation, so RTL fabric work and PHY-option survey work share a single interface reference.

Sections to include:

Purpose and scope (decouple PHY from upper layers per Section 13.3)
Bundle signals (placeholder table: tx_data, rx_data, tx_valid, rx_valid, lane_status, reset/init handshake, error flags, calibration controls)
Lane configuration (lane count and per-lane width left as TBD ranges)
Clock and reset domains (PHY-side vs upper-layer)
Init/training sequence requirements (state-machine sketch only, no timing numbers)
Error reporting (BER reporting hook for Section 12.4 verification)
Behavioral-PHY simulation contract (how PopLinkPHY_Behavioral.scala must satisfy this interface)
Open questions (lane count, target Gb/s — defer to PHY options survey)

Acceptance criteria

docs/spec/poplink-phy-if.md exists with the sections above
Status: Draft skeleton + Owner: TBD header
Each section has TODO markers and short intent description
Bundle-signal table has placeholder rows (no fabricated widths/timings)
Explicitly cross-references the open PHY options survey work and the InterChipFabric / PopLinkPHY_Behavioral skeleton issues
No commitments on lane count or Gb/s — those depend on PHY option selection
References PLAN.md Sections 13.3, 13.4, 12.4 explicitly

Plan refs

Section 13.3 (PopLinkPHYIO bundle), Section 13.4 (Phase 1 PHY deliverable #2), Section 12.4 (BER verification expectations)

Notes

Spec scaffold only — final widths, lane counts, and timing close depend on PHY option selection (academic vs commercial IP). Keep skeleton vendor-neutral; the behavioral RTL implementation and the research report docs/phy/phy-options.md are tracked under separate issues.

## Goal Create the PopLink PHY interface spec skeleton at `docs/spec/poplink-phy-if.md`, named explicitly as Phase 1 PHY deliverable #2 in PLAN.md Section 13.4. The spec describes the `PopLinkPHYIO` Chisel bundle contract that decouples upper-layer fabric logic from the analog PHY implementation, so RTL fabric work and PHY-option survey work share a single interface reference. Sections to include: - Purpose and scope (decouple PHY from upper layers per Section 13.3) - Bundle signals (placeholder table: tx_data, rx_data, tx_valid, rx_valid, lane_status, reset/init handshake, error flags, calibration controls) - Lane configuration (lane count and per-lane width left as TBD ranges) - Clock and reset domains (PHY-side vs upper-layer) - Init/training sequence requirements (state-machine sketch only, no timing numbers) - Error reporting (BER reporting hook for Section 12.4 verification) - Behavioral-PHY simulation contract (how `PopLinkPHY_Behavioral.scala` must satisfy this interface) - Open questions (lane count, target Gb/s — defer to PHY options survey) ## Acceptance criteria - [ ] `docs/spec/poplink-phy-if.md` exists with the sections above - [ ] `Status: Draft skeleton` + `Owner: TBD` header - [ ] Each section has `TODO` markers and short intent description - [ ] Bundle-signal table has placeholder rows (no fabricated widths/timings) - [ ] Explicitly cross-references the open PHY options survey work and the InterChipFabric / PopLinkPHY_Behavioral skeleton issues - [ ] No commitments on lane count or Gb/s — those depend on PHY option selection - [ ] References PLAN.md Sections 13.3, 13.4, 12.4 explicitly ## Plan refs Section 13.3 (PopLinkPHYIO bundle), Section 13.4 (Phase 1 PHY deliverable #2), Section 12.4 (BER verification expectations) ## Notes Spec scaffold only — final widths, lane counts, and timing close depend on PHY option selection (academic vs commercial IP). Keep skeleton vendor-neutral; the behavioral RTL implementation and the research report `docs/phy/phy-options.md` are tracked under separate issues.

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2026-05-26 15:05:09 -03:00

navigator commented

2026-05-26 15:05:37 -03:00

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navigator commented

2026-05-26 15:06:25 -03:00

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The spec file `docs/spec/poplink-phy-if.md` already exists on `main` and satisfies every acceptance criterion in this issue. It was committed by PR #75 (`20015d8 docs(spec): draft PopLink PHY interface skeleton (poplink-phy-if.md)`).\n\nVerified criteria on current `main`:\n\n- File exists at `docs/spec/poplink-phy-if.md` (171 lines).\n- Header (lines 6-7): `**Status:** Draft skeleton` / `**Owner:** TBD`.\n- All 8 sections present: Purpose & scope (§1), Bundle signals (§2), Lane configuration (§3), Clock/reset domains (§4), Init/training sequence (§5), Error reporting (§6), Behavioral-PHY simulation contract (§7), Open questions (§8).\n- Every section ends with a `TODO` marker (§§1 line 33, §2 line 63, §3 line 80, §4 line 93, §5 line 113, §6 line 126, §7 line 143, §8 line 159).\n- Bundle-signal table at §2 lists 11 placeholder signal classes; all widths marked `TBD`; no fabricated numbers.\n- Cross-references: InterChipFabric (line 11), `PopLinkPHY_Behavioral.SPEC.md` + issue #51 (lines 9, 25, 132, 143, 169), PHY options survey issue #6 (lines 9, 11, 30, 33, 63, 71, 80, 88, 113, 151, 170), ADR-009 (lines 9, 17).\n- No commitments on lane count or Gb/s: §3 explicitly defers N/W/R; §8 §§1-3 list them as open questions.\n- PLAN.md refs §13.3, §13.4, §12.4 explicit in the header (line 8), in-text (lines 17, 24, 119, 121, 124, 132), and in the References section (line 165).\n\nRecommendation: close this issue as duplicate of #75 (merged). No PR opened.

The spec file `docs/spec/poplink-phy-if.md` already exists on `main` and satisfies every acceptance criterion in this issue. It was committed by PR #75 (`20015d8 docs(spec): draft PopLink PHY interface skeleton (poplink-phy-if.md)`).\n\nVerified criteria on current `main`:\n\n- File exists at `docs/spec/poplink-phy-if.md` (171 lines).\n- Header (lines 6-7): `**Status:** Draft skeleton` / `**Owner:** TBD`.\n- All 8 sections present: Purpose & scope (§1), Bundle signals (§2), Lane configuration (§3), Clock/reset domains (§4), Init/training sequence (§5), Error reporting (§6), Behavioral-PHY simulation contract (§7), Open questions (§8).\n- Every section ends with a `TODO` marker (§§1 line 33, §2 line 63, §3 line 80, §4 line 93, §5 line 113, §6 line 126, §7 line 143, §8 line 159).\n- Bundle-signal table at §2 lists 11 placeholder signal classes; all widths marked `TBD`; no fabricated numbers.\n- Cross-references: InterChipFabric (line 11), `PopLinkPHY_Behavioral.SPEC.md` + issue #51 (lines 9, 25, 132, 143, 169), PHY options survey issue #6 (lines 9, 11, 30, 33, 63, 71, 80, 88, 113, 151, 170), ADR-009 (lines 9, 17).\n- No commitments on lane count or Gb/s: §3 explicitly defers N/W/R; §8 §§1-3 list them as open questions.\n- PLAN.md refs §13.3, §13.4, §12.4 explicit in the header (line 8), in-text (lines 17, 24, 119, 121, 124, 132), and in the References section (line 165).\n\nRecommendation: close this issue as duplicate of #75 (merged). No PR opened.

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2026-05-26 15:06:40 -03:00

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