rtl: PopLinkPHY_Behavioral v1 — configurable line-rate + BER injection + drop knobs #113

New issue

Closed

opened 2026-05-26 18:12:06 -03:00 by navigator · 4 comments

navigator commented

2026-05-26 18:12:06 -03:00

Owner

Goal

Implement v1 behaviour of PopLinkPHY_Behavioral per Draft SPEC at rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md (#95). Skeleton (#106) lands linkUp. This issue lands the simulation-only configurable line-rate / latency / BER / drop knobs needed for §12.4 ARQ stress.

Scope — strictly what the Draft SPEC pins

Constructor: class PopLinkPHY_Behavioral(numLanes: Int = 4, symbolWidthBits: Int = 8, latencyCycles: Int = 4)
IO surface adds: per-lane tx = Input(Vec(numLanes, UInt(symbolWidthBits.W))), rx = Output(Vec(numLanes, UInt(symbolWidthBits.W))), plus DPI-style control inputs berDenominator = Input(UInt(32.W)) (0 = clean, 1 = 1/1, N = 1/N flips per symbol) and dropEvery = Input(UInt(32.W)) (0 = no drops).
Behavior: shift tx through a latencyCycles-deep delay line, XOR a random 1-bit error onto the output symbol when an LFSR matches the berDenominator modulus, drop the symbol entirely when an internal counter wraps at dropEvery. linkUp := true.B always (no training in behavioral model).
Non-synthesisable: file MUST carry a // synthesis translate_off guard around the body.

Open Questions — do NOT invent

Lane training protocol — Open (§Interface). linkUp stays a constant.
BER reproducibility seed mechanism — Open (§Behavior). Use a fixed LFSR seed 0xACE1, annotate that production should accept a seed input.

Acceptance criteria

rtl/src/pop/PopLinkPHY_Behavioral.scala materialises the delay-line + BER injector + drop counter
rtl/tests/PopLinkPHY_Behavioral/PopLinkPHY_BehavioralSpec.scala extended with three scenarios:
- berDenominator=0, dropEvery=0: bit-exact passthrough after latencyCycles
- berDenominator=10: ~10% symbol flip rate over a 1000-cycle window (loose bound: 60–140 flips)
- dropEvery=8: every 8th symbol disappears
sbt -no-colors test green
// synthesis translate_off guards around all chisel3.experimental.RawClock-style or random sources

Plan refs

PLAN.md §12.4 (ARQ stress), §13.4 (PHY behavioral deliverable); ADR-009 (PopLink fabric).

## Goal Implement v1 behaviour of `PopLinkPHY_Behavioral` per Draft SPEC at `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` (#95). Skeleton (#106) lands `linkUp`. This issue lands the simulation-only configurable line-rate / latency / BER / drop knobs needed for §12.4 ARQ stress. ## Scope — strictly what the Draft SPEC pins - Constructor: `class PopLinkPHY_Behavioral(numLanes: Int = 4, symbolWidthBits: Int = 8, latencyCycles: Int = 4)` - IO surface adds: per-lane `tx = Input(Vec(numLanes, UInt(symbolWidthBits.W)))`, `rx = Output(Vec(numLanes, UInt(symbolWidthBits.W)))`, plus DPI-style control inputs `berDenominator = Input(UInt(32.W))` (0 = clean, 1 = 1/1, N = 1/N flips per symbol) and `dropEvery = Input(UInt(32.W))` (0 = no drops). - Behavior: shift `tx` through a `latencyCycles`-deep delay line, XOR a random 1-bit error onto the output symbol when an LFSR matches the `berDenominator` modulus, drop the symbol entirely when an internal counter wraps at `dropEvery`. `linkUp := true.B` always (no training in behavioral model). - Non-synthesisable: file MUST carry a `// synthesis translate_off` guard around the body. ## Open Questions — do NOT invent - Lane training protocol — Open (§Interface). `linkUp` stays a constant. - BER reproducibility seed mechanism — Open (§Behavior). Use a fixed LFSR seed `0xACE1`, annotate that production should accept a seed input. ## Acceptance criteria - [ ] `rtl/src/pop/PopLinkPHY_Behavioral.scala` materialises the delay-line + BER injector + drop counter - [ ] `rtl/tests/PopLinkPHY_Behavioral/PopLinkPHY_BehavioralSpec.scala` extended with three scenarios: - `berDenominator=0, dropEvery=0`: bit-exact passthrough after `latencyCycles` - `berDenominator=10`: ~10% symbol flip rate over a 1000-cycle window (loose bound: 60–140 flips) - `dropEvery=8`: every 8th symbol disappears - [ ] `sbt -no-colors test` green - [ ] `// synthesis translate_off` guards around all `chisel3.experimental.RawClock`-style or random sources ## Plan refs PLAN.md §12.4 (ARQ stress), §13.4 (PHY behavioral deliverable); ADR-009 (PopLink fabric).