rtl: PopLinkPHY_Behavioral v1 — configurable line-rate + BER + drop knobs #116

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Summary

Implements PopLinkPHY_Behavioral v1 per rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md (Status: Draft) — fills in the delay line, BER injector and drop counter behind the existing PopLinkPHYIO surface so PLAN.md §12.4 ARQ stress can drive the fabric against a deterministic stand-in PHY.
New constructor parameters: numLanes (default 4), symbolWidthBits (default 8), latencyCycles (default 4).
Adds per-lane tx/rx Vec data fields, plus DPI-style runtime knobs berDenominator (32-bit) and dropEvery (32-bit). BER knobs are deliberately kept out of PopLinkPHYIO so the production-PHY swap stays shape-identical per SPEC §Invariants.
32-bit Fibonacci LFSR seeded at 0xACE1 (taps 31/21/1/0) drives the 1-bit-flip random source. Drop wins over BER for the same cycle. linkUp := true.B always.
// synthesis translate_off / translate_on guard around the sim-only body per SPEC §Invariants ("Never synthesised").

Test plan

sbt test green locally (17/17, including 4 new PopLinkPHY_BehavioralSpec scenarios).
- clean passthrough at berDenominator=0, dropEvery=0 after latencyCycles.
- berDenominator=10 → 60–140 symbol flips over 1000 cycles (loose bound; deterministic LFSR seed makes the count reproducible).
- dropEvery=8 → exactly 10 drops over 80 cycles (window / dropEvery).
- skeleton elaborate check preserved.
PR Approver triage.

Closes #113.

## Summary - Implements PopLinkPHY_Behavioral v1 per `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` (Status: Draft) — fills in the delay line, BER injector and drop counter behind the existing `PopLinkPHYIO` surface so PLAN.md §12.4 ARQ stress can drive the fabric against a deterministic stand-in PHY. - New constructor parameters: `numLanes` (default 4), `symbolWidthBits` (default 8), `latencyCycles` (default 4). - Adds per-lane `tx`/`rx` Vec data fields, plus DPI-style runtime knobs `berDenominator` (32-bit) and `dropEvery` (32-bit). BER knobs are deliberately kept out of `PopLinkPHYIO` so the production-PHY swap stays shape-identical per SPEC §Invariants. - 32-bit Fibonacci LFSR seeded at `0xACE1` (taps 31/21/1/0) drives the 1-bit-flip random source. Drop wins over BER for the same cycle. `linkUp := true.B` always. - `// synthesis translate_off` / `translate_on` guard around the sim-only body per SPEC §Invariants ("Never synthesised"). ## Test plan - [x] `sbt test` green locally (17/17, including 4 new `PopLinkPHY_BehavioralSpec` scenarios). - clean passthrough at `berDenominator=0, dropEvery=0` after `latencyCycles`. - `berDenominator=10` → 60–140 symbol flips over 1000 cycles (loose bound; deterministic LFSR seed makes the count reproducible). - `dropEvery=8` → exactly 10 drops over 80 cycles (`window / dropEvery`). - skeleton `elaborate` check preserved. - [ ] PR Approver triage. Closes #113.

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rtl: PopLinkPHY_Behavioral v1 — configurable line-rate + BER + drop knobs

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484183bbe7

Lands the v1 behaviour behind the PopLinkPHYIO surface so InterChipFabric
can drive the §12.4 ARQ stress against a deterministic stand-in PHY while
the production PHY-option-selection track (PLAN.md §13.2) runs in
parallel. The skeleton (#106) elaborated only; this PR fills in the
delay line, BER injector and drop counter the SPEC §Behavior pins.

- numLanes / symbolWidthBits / latencyCycles constructor parameters.
- Per-lane tx Vec input, per-lane rx Vec output.
- berDenominator (0=clean, 1=every symbol, N=~1/N) and dropEvery
  (0=no drops) DPI-style runtime knobs, deliberately kept out of
  PopLinkPHYIO so the production PHY swap stays shape-identical.
- 32-bit Fibonacci LFSR (seed 0xACE1, fixed) driving the bit-flip
  source; production seed input tracked as a SPEC §Behavior Open
  question. Drop wins over BER for the same cycle.
- linkUp tied true (no training in the behavioral model).
- // synthesis translate_off guard around the sim-only body per
  SPEC §Invariants.

Three new chiseltest scenarios pin the contract:
  - clean passthrough after latencyCycles
  - berDenominator=10 → loose 60–140 flips over 1000 cycles
  - dropEvery=8 → every 8th symbol disappears

Closes #113.

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VERDICT: PASS

PR #116 lifts PopLinkPHY_Behavioral from the elaborate-only skeleton (PR #106) into a v1 with configurable line-rate, BER injection, and drop knobs — exactly the SPEC §Behavior items it claims to deliver. Mechanical guardrails pass: existing SPDX headers preserved (CHARRUA-1.2 source, AGPL-3.0-or-later test), both files in package pop, no AI/Anthropic attribution, no off-limits paths, scope matches Issue #113. Rule 4 is handled with care: the canonical PopLinkPHYIO class is preserved (consumed Flipped by InterChipFabric on its PHY-facing side) and gets concrete tx.data / rx.data Vecs parameterised on (numLanes, symbolWidthBits); the module's IO inlines the same fields plus sim-only DPI-style berDenominator / dropEvery knobs that are explicitly NOT part of PopLinkPHYIO, preserving the SPEC §Invariants "Same public PopLinkPHYIO bundle as the production PHY" — a swap of behavioral → production PHY remains a Chisel Module substitution, not an upper-layer rewrite. SPEC §Invariants "Never synthesised — sim-only guard required" is satisfied with // synthesis translate_off / translate_on directives around the LFSR / delay-line body; default tie-offs sit outside the guard so a stray synthesis attempt would fail with unconnected rx.data, which is the right fail-safe. Rule 7 is meticulously handled: numLanes=4 matches PLAN.md §3.3 Edu envelope (verbatim quoted from PR #91/#95); symbolWidthBits=8 is annotated as "byte-symbol default the SPEC §Interface Open question leaves until the PHY-option closes"; latencyCycles=4 is annotated as "SPEC §Interface Open question"; LFSR seed 0xACE1 is explicitly flagged with "production PHY must accept a seed input (TBD)" matching the SPEC §Behavior reproducibility-seed open framing; the LFSR taps 31, 21, 1, 0 correctly encode the well-known maximum-period polynomial x³² + x²² + x² + x + 1; linkUp := true.B is annotated "no training in the behavioral model" matching SPEC §Behavior's degenerate-FSM framing. The four test scenarios map cleanly to SPEC §Behavior invariants: bit-exact passthrough verifies the BER=0 invariant after latencyCycles, the BER-injection test verifies the §12.4 ARQ-stress driver path with a loose 60–140 / 1000-cycle bound at berDenominator=10 (close to 10% expectation with reproducible-LFSR tolerance), and the drop test verifies the SPEC §Behavior drop-knob semantics with deterministic 10 drops over 80 cycles at dropEvery=8. The "drop wins over BER for the same cycle" precedence is documented inline. No fabricated VC counts, lane rates, or vendor commitments.

Findings

None.

**VERDICT:** PASS PR #116 lifts `PopLinkPHY_Behavioral` from the elaborate-only skeleton (PR #106) into a v1 with configurable line-rate, BER injection, and drop knobs — exactly the SPEC §Behavior items it claims to deliver. Mechanical guardrails pass: existing SPDX headers preserved (`CHARRUA-1.2` source, `AGPL-3.0-or-later` test), both files in `package pop`, no AI/Anthropic attribution, no off-limits paths, scope matches Issue #113. Rule 4 is handled with care: the canonical `PopLinkPHYIO` class is preserved (consumed `Flipped` by `InterChipFabric` on its PHY-facing side) and gets concrete `tx.data` / `rx.data` Vecs parameterised on `(numLanes, symbolWidthBits)`; the module's IO inlines the same fields plus sim-only DPI-style `berDenominator` / `dropEvery` knobs that are explicitly NOT part of `PopLinkPHYIO`, preserving the SPEC §Invariants "Same public PopLinkPHYIO bundle as the production PHY" — a swap of behavioral → production PHY remains a Chisel `Module` substitution, not an upper-layer rewrite. SPEC §Invariants "Never synthesised — sim-only guard required" is satisfied with `// synthesis translate_off` / `translate_on` directives around the LFSR / delay-line body; default tie-offs sit outside the guard so a stray synthesis attempt would fail with unconnected `rx.data`, which is the right fail-safe. Rule 7 is meticulously handled: `numLanes=4` matches PLAN.md §3.3 Edu envelope (verbatim quoted from PR #91/#95); `symbolWidthBits=8` is annotated as "byte-symbol default the SPEC §Interface Open question leaves until the PHY-option closes"; `latencyCycles=4` is annotated as "SPEC §Interface Open question"; LFSR seed `0xACE1` is explicitly flagged with "production PHY must accept a seed input (TBD)" matching the SPEC §Behavior reproducibility-seed open framing; the LFSR taps `31, 21, 1, 0` correctly encode the well-known maximum-period polynomial `x³² + x²² + x² + x + 1`; `linkUp := true.B` is annotated "no training in the behavioral model" matching SPEC §Behavior's degenerate-FSM framing. The four test scenarios map cleanly to SPEC §Behavior invariants: bit-exact passthrough verifies the `BER=0` invariant after `latencyCycles`, the BER-injection test verifies the §12.4 ARQ-stress driver path with a loose 60–140 / 1000-cycle bound at `berDenominator=10` (close to 10% expectation with reproducible-LFSR tolerance), and the drop test verifies the SPEC §Behavior drop-knob semantics with deterministic 10 drops over 80 cycles at `dropEvery=8`. The "drop wins over BER for the same cycle" precedence is documented inline. No fabricated VC counts, lane rates, or vendor commitments. ## Findings _None._

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