#124 - rtl: InterChipFabric v1 — XY-routed 2D-torus + credit-based flow control - Fluid/fluidpop-v1 - Git PopSolutions: Pop.Coop

navigator commented

2026-06-18 02:12:50 -03:00

Owner

Goal

Implement v1 behaviour of InterChipFabric per Draft SPEC at rtl/src/pop/specs/InterChipFabric.SPEC.md (#91). The skeleton (#82) lands empty ports, credits, phy, csr bundles. This issue lands the actual XY-routed 2D-torus fabric endpoint using the just-landed InterGemminiXbar (#115) as the local crossbar pattern and the PopLinkPHY_Behavioral v1 (#116) as the PHY attach.

Scope — strictly what the Draft SPEC pins

Constructor: class InterChipFabric(numPorts: Int = 4, flitBits: Int = 64, numVCs: Int = 2) — port count fixed at 4 (N/S/E/W per ADR-010); flit width and VC count parameterised, default 64/2.
IO: 4 PopLink ports, per-port credit-based flow control (one credit counter per VC per port), CSR surface for routing-table programming and per-port error counters.
Behavior: dimension-ordered routing (X first then Y) per ADR-010; credit-based per-VC back-pressure; per-port quad routing decision (look up dest chip-id in CSR table, drop onto matching output port).
Quiescence: drain on csr.fabricStop mirrors PopRoCCRouter quiescence FSM pattern.

Open Questions — do NOT invent

Concrete flit header layout — Open per §Interface. Use opaque UInt(flitBits.W) payload + an Output(UInt(log2Ceil(8).W)) destChipId field (8 chips total per ADR-008), annotate as Open.
CSR address map — Open. Reuse the same opaque UInt(32.W) addr/data CSR pattern from PopRoCCRouter v1.
VC arbitration policy — Open. Default to round-robin between VCs at output port.

Acceptance criteria

rtl/src/pop/InterChipFabric.scala body materialises 4-port input FIFOs + XY routing + per-VC credit counters + output arbitration
rtl/tests/InterChipFabric/InterChipFabricSpec.scala extended with three scenarios:
- Single flit routed N→S correctly (1-hop)
- Single flit routed E→W with one intermediate hop (2-hop diameter per ADR-010)
- Sustained back-pressure on one egress port does not block other 3 (no-deadlock)
sbt -no-colors test green; tests parameterised on numVCs ∈ {1, 2}
No fabricated flit header semantics

Plan refs

PLAN.md §8.2, §12.3, §12.4; ADR-009 (PopLink fabric), ADR-010 (2D-torus topology).

## Goal Implement v1 behaviour of `InterChipFabric` per Draft SPEC at `rtl/src/pop/specs/InterChipFabric.SPEC.md` (#91). The skeleton (#82) lands empty `ports`, `credits`, `phy`, `csr` bundles. This issue lands the actual XY-routed 2D-torus fabric endpoint using the just-landed `InterGemminiXbar` (#115) as the local crossbar pattern and the `PopLinkPHY_Behavioral` v1 (#116) as the PHY attach. ## Scope — strictly what the Draft SPEC pins - Constructor: `class InterChipFabric(numPorts: Int = 4, flitBits: Int = 64, numVCs: Int = 2)` — port count fixed at 4 (N/S/E/W per ADR-010); flit width and VC count parameterised, default 64/2. - IO: 4 PopLink ports, per-port credit-based flow control (one credit counter per VC per port), CSR surface for routing-table programming and per-port error counters. - Behavior: dimension-ordered routing (X first then Y) per ADR-010; credit-based per-VC back-pressure; per-port quad routing decision (look up dest chip-id in CSR table, drop onto matching output port). - Quiescence: drain on `csr.fabricStop` mirrors `PopRoCCRouter` quiescence FSM pattern. ## Open Questions — do NOT invent - Concrete flit header layout — Open per §Interface. Use opaque `UInt(flitBits.W)` payload + an `Output(UInt(log2Ceil(8).W))` destChipId field (8 chips total per ADR-008), annotate as Open. - CSR address map — Open. Reuse the same opaque `UInt(32.W)` addr/data CSR pattern from PopRoCCRouter v1. - VC arbitration policy — Open. Default to round-robin between VCs at output port. ## Acceptance criteria - [ ] `rtl/src/pop/InterChipFabric.scala` body materialises 4-port input FIFOs + XY routing + per-VC credit counters + output arbitration - [ ] `rtl/tests/InterChipFabric/InterChipFabricSpec.scala` extended with three scenarios: - Single flit routed N→S correctly (1-hop) - Single flit routed E→W with one intermediate hop (2-hop diameter per ADR-010) - Sustained back-pressure on one egress port does not block other 3 (no-deadlock) - [ ] `sbt -no-colors test` green; tests parameterised on `numVCs ∈ {1, 2}` - [ ] No fabricated flit header semantics ## Plan refs PLAN.md §8.2, §12.3, §12.4; ADR-009 (PopLink fabric), ADR-010 (2D-torus topology).