#125 - rtl: FluidPopSoC v1 — top-level integration of all v1 submodules - Fluid/fluidpop-v1 - Git PopSolutions: Pop.Coop

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2026-06-18 02:12:50 -03:00

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Goal

Implement v1 top-level integration of FluidPopSoC per Draft SPEC at rtl/src/pop/specs/FluidPopSoC.SPEC.md (#87). The skeleton (#83) lands an empty top module. This issue lands the first end-to-end wire-up of all the v1 modules that have landed: PopRoCCRouter (#107), PopSoCConfig (#108), PopLinkPHY_Behavioral (#116), InterGemminiXbar (#115), MultiGemminiCluster v1 (#114, will land before this), InterChipFabric v1 (sibling issue, will land before this), PCIeHostBridge (skeleton, master variant only).

Scope — strictly what the Draft SPEC pins

Constructor reads PopSoCConfig Field keys: TileCountKey, FabricPortCountKey, IsMasterKey, VariantKey.
Instantiate: 1× MultiGemminiCluster(N=TileCountKey), 1× InterChipFabric(numPorts=FabricPortCountKey), 4× PopLinkPHY_Behavioral (one per PopLink port), 1× PopRoCCRouter, conditionally 1× PCIeHostBridge (only when IsMasterKey == true).
Wire: PopRoCCRouter ↔ MultiGemminiCluster (per-tile fan-out), MultiGemminiCluster ↔ InterChipFabric (PopLink-bound port), InterChipFabric ↔ each PopLinkPHY_Behavioral (per-port).
Add numCores: Int = 2 (ADR-006 Edu default), instantiate that many Rocket-shaped RoCC cmd/resp ports surfaced to top IO.

Open Questions — do NOT invent

DDR5 / mem port — Open per §Interface. Leave // TBD per SPEC §Interface — DDR5 mem port as a top-level commented // val mem = ???.
Rocket core instantiation — Open. Use top-level Vec(numCores, Decoupled(...)) RoCC ports rather than instantiating Rocket directly (Chipyard pin issue per #46 series).
BMC sideband, JTAG — Open. Surface as opaque opaque Input(UInt(32.W)) placeholder, annotate.

Acceptance criteria

rtl/src/pop/FluidPopSoC.scala body instantiates and wires all the v1 submodules above
rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala extended with two scenarios:
- FluidPopMasterConfig elaborates AND instantiates PCIeHostBridge
- FluidPopSlaveConfig elaborates AND skips PCIeHostBridge
sbt -no-colors test green
No fabricated DDR5 / Rocket-internal widths
No edits outside rtl/src/pop/FluidPopSoC.scala, rtl/tests/FluidPopSoC/

Blocked on

#114 (MultiGemminiCluster v1) — must land first
This issue's sibling InterChipFabric v1 — must land first

Plan refs

PLAN.md §8.2 (full module list); ADR-001, ADR-006, ADR-008, ADR-010.

## Goal Implement v1 top-level integration of `FluidPopSoC` per Draft SPEC at `rtl/src/pop/specs/FluidPopSoC.SPEC.md` (#87). The skeleton (#83) lands an empty top module. This issue lands the **first end-to-end wire-up** of all the v1 modules that have landed: `PopRoCCRouter` (#107), `PopSoCConfig` (#108), `PopLinkPHY_Behavioral` (#116), `InterGemminiXbar` (#115), `MultiGemminiCluster` v1 (#114, will land before this), `InterChipFabric` v1 (sibling issue, will land before this), `PCIeHostBridge` (skeleton, master variant only). ## Scope — strictly what the Draft SPEC pins - Constructor reads `PopSoCConfig` Field keys: `TileCountKey`, `FabricPortCountKey`, `IsMasterKey`, `VariantKey`. - Instantiate: 1× `MultiGemminiCluster(N=TileCountKey)`, 1× `InterChipFabric(numPorts=FabricPortCountKey)`, 4× `PopLinkPHY_Behavioral` (one per PopLink port), 1× `PopRoCCRouter`, conditionally 1× `PCIeHostBridge` (only when `IsMasterKey == true`). - Wire: PopRoCCRouter ↔ MultiGemminiCluster (per-tile fan-out), MultiGemminiCluster ↔ InterChipFabric (PopLink-bound port), InterChipFabric ↔ each PopLinkPHY_Behavioral (per-port). - Add `numCores: Int = 2` (ADR-006 Edu default), instantiate that many Rocket-shaped RoCC `cmd`/`resp` ports surfaced to top IO. ## Open Questions — do NOT invent - DDR5 / mem port — Open per §Interface. Leave `// TBD per SPEC §Interface — DDR5 mem port` as a top-level commented `// val mem = ???`. - Rocket core instantiation — Open. Use top-level `Vec(numCores, Decoupled(...))` RoCC ports rather than instantiating Rocket directly (Chipyard pin issue per #46 series). - BMC sideband, JTAG — Open. Surface as opaque opaque `Input(UInt(32.W))` placeholder, annotate. ## Acceptance criteria - [ ] `rtl/src/pop/FluidPopSoC.scala` body instantiates and wires all the v1 submodules above - [ ] `rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala` extended with two scenarios: - `FluidPopMasterConfig` elaborates AND instantiates `PCIeHostBridge` - `FluidPopSlaveConfig` elaborates AND skips `PCIeHostBridge` - [ ] `sbt -no-colors test` green - [ ] No fabricated DDR5 / Rocket-internal widths - [ ] No edits outside `rtl/src/pop/FluidPopSoC.scala`, `rtl/tests/FluidPopSoC/` ## Blocked on - #114 (MultiGemminiCluster v1) — must land first - This issue's sibling InterChipFabric v1 — must land first ## Plan refs PLAN.md §8.2 (full module list); ADR-001, ADR-006, ADR-008, ADR-010.