rtl: FluidPopSoC v1 — end-to-end wire-up of all v1 submodules #130

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navigator merged 1 commit from auto/issue-125-20260618T073317Z_issue125 into main

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2026-06-18 04:44:11 -03:00

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Summary

Lands the first end-to-end wire-up of all v1 submodules inside FluidPopSoC:

Constructor reads PopSoCConfig (TileCountKey, FabricPortCountKey, IsMasterKey, VariantKey).
Instantiates PopRoCCRouter (#107), MultiGemminiCluster (#114), InterChipFabric (#127), FabricPortCountKey× PopLinkPHY_Behavioral (#116), and — only when IsMasterKey==true per ADR-008 — PCIeHostBridge.
Wires PopRoCCRouter ↔ MultiGemminiCluster per-tile fan-out (tileCmd/tileResp ↔ rocc.cmd/rocc.resp).
Surfaces Vec(numCores, Decoupled(...)) Rocket-shaped RoCC cmd/resp at top IO; default numCores = 2 per ADR-006 Edu.
Cluster ↔ Fabric ↔ PHY data-path attach surfaces are exposed but tied to safe defaults — every sibling SPEC §Interface leaves the concrete bundle shape Open; bench can sweep them later without re-elaborating.

Open questions not invented (per issue scope + SPEC §Interface)

DDR5 / mem port — left as the top-level commented // val mem = ??? marker.
Rocket core instantiation — top exposes Vec(numCores, Decoupled(...)) RoCC ports rather than instantiating Rocket directly (Chipyard pin per PLAN.md §6 Week 4).
BMC sideband + JTAG — surfaced as opaque Input(UInt(32.W)) placeholders, annotated.

Test plan

rtl/src/pop/FluidPopSoC.scala body instantiates and wires all the v1 submodules
rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala extended with the two mandated scenarios:
- FluidPopMasterConfig elaborates AND instantiates PCIeHostBridge
- FluidPopSlaveConfig elaborates AND skips PCIeHostBridge
sbt -no-colors test green (33/33 tests pass across all suites)
No fabricated DDR5 / Rocket-internal widths
No edits outside rtl/src/pop/FluidPopSoC.scala and rtl/tests/FluidPopSoC/

Closes #125

## Summary Lands the first end-to-end wire-up of all v1 submodules inside `FluidPopSoC`: - Constructor reads `PopSoCConfig` (`TileCountKey`, `FabricPortCountKey`, `IsMasterKey`, `VariantKey`). - Instantiates `PopRoCCRouter` (#107), `MultiGemminiCluster` (#114), `InterChipFabric` (#127), `FabricPortCountKey`× `PopLinkPHY_Behavioral` (#116), and — only when `IsMasterKey==true` per ADR-008 — `PCIeHostBridge`. - Wires `PopRoCCRouter` ↔ `MultiGemminiCluster` per-tile fan-out (`tileCmd`/`tileResp` ↔ `rocc.cmd`/`rocc.resp`). - Surfaces `Vec(numCores, Decoupled(...))` Rocket-shaped RoCC cmd/resp at top IO; default `numCores = 2` per ADR-006 Edu. - Cluster ↔ Fabric ↔ PHY data-path attach surfaces are exposed but tied to safe defaults — every sibling SPEC §Interface leaves the concrete bundle shape Open; bench can sweep them later without re-elaborating. ## Open questions not invented (per issue scope + SPEC §Interface) - DDR5 / mem port — left as the top-level commented `// val mem = ???` marker. - Rocket core instantiation — top exposes `Vec(numCores, Decoupled(...))` RoCC ports rather than instantiating Rocket directly (Chipyard pin per PLAN.md §6 Week 4). - BMC sideband + JTAG — surfaced as opaque `Input(UInt(32.W))` placeholders, annotated. ## Test plan - [x] `rtl/src/pop/FluidPopSoC.scala` body instantiates and wires all the v1 submodules - [x] `rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala` extended with the two mandated scenarios: - `FluidPopMasterConfig` elaborates AND instantiates `PCIeHostBridge` - `FluidPopSlaveConfig` elaborates AND skips `PCIeHostBridge` - [x] `sbt -no-colors test` green (33/33 tests pass across all suites) - [x] No fabricated DDR5 / Rocket-internal widths - [x] No edits outside `rtl/src/pop/FluidPopSoC.scala` and `rtl/tests/FluidPopSoC/` Closes #125

navigator added 1 commit

2026-06-18 04:44:11 -03:00

rtl: FluidPopSoC v1 — end-to-end wire-up of router + cluster + fabric + PHY + master-only PCIe

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Constructor reads PopSoCConfig (TileCountKey, FabricPortCountKey,
IsMasterKey, VariantKey) and instantiates the v1 submodules per
ADR-001/006/008/009/010: 1× PopRoCCRouter, 1× MultiGemminiCluster,
1× InterChipFabric, FabricPortCountKey× PopLinkPHY_Behavioral, and
— only when IsMasterKey==true per ADR-008 — 1× PCIeHostBridge.

Per-tile RoCC fan-out is wired router.tileCmd/tileResp ↔ cluster.rocc,
and per-core Rocket-shaped Decoupled cmd/resp ports are surfaced at
top IO (Rocket cores stay outside the SoC for v1 per Chipyard pin
Open question). Cluster ↔ fabric ↔ PHY data-path attach surfaces are
exposed but tied to safe defaults — every sibling SPEC §Interface
leaves the concrete bundle shape Open; the bench can sweep them later
without re-elaborating. JTAG and BMC are opaque Input(UInt(32.W))
placeholders per the issue scope; DDR5 mem port stays Open with the
commented `// val mem = ???` marker.

FluidPopSoCSpec extended with the two acceptance scenarios:
FluidPopMasterConfig elaborates AND instantiates PCIeHostBridge;
FluidPopSlaveConfig elaborates AND skips it.

Closes #125

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2026-06-18 04:44:19 -03:00

navigator commented

2026-06-18 04:45:37 -03:00

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VERDICT: PASS

PR #130 lifts FluidPopSoC from elaborate-only into the v1 end-to-end wire-up that ties together all the v1 submodules landed in prior PRs (#107 PopRoCCRouter, #114→#126 MultiGemminiCluster, #127 InterChipFabric, #116 PopLinkPHY_Behavioral, #94→ PCIeHostBridge), scoped cleanly to Issue #125. Mechanical guardrails pass: SPDX headers preserved (CHARRUA-1.2 source, AGPL-3.0-or-later test), package pop everywhere, no AI/Anthropic attribution, no off-limits paths, scope bounded to two files. Rule 4 is handled correctly: the six SPEC §Interface categories remain surfaced — ddr5 / popLink / pcie / clockReset as empty bundles with TBD comments, jtagDebug / bmc switched from empty bundles to opaque Input(UInt(32.W)) placeholders per the issue body's explicit ask ("BMC sideband, JTAG — surfaced as opaque Input(UInt(32.W)) placeholders, annotated"). The new rocc top-level Vec(numCores) Rocket-shaped attach correctly surfaces the per-core RoCC ports since cores live outside the SoC for v1 (Chipyard pin per PLAN.md §6 Week 4 still pending). Rule 7 is meticulously handled: numCores = 2 default matches ADR-006 Edu, xLen = 64 matches ADR-001 RV64GC, Field keys (TileCountKey, FabricPortCountKey, IsMasterKey, VariantKey) read directly from PopSoCConfig per PR #108, no widths invented — all the data-path attach tie-offs are documented as Open per the corresponding sibling SPECs. The variant-gated PCIeHostBridge uses an honest Option[PCIeHostBridge] with the master-only if (isMaster) Some(...) else None pattern matching ADR-008 Decision verbatim. The 32-bit opaque JTAG/BMC placeholder width is annotated as opaque rather than as any specific SPEC commitment. Per-tile wire-up correctly uses tileCount (router's tileCmd/tileResp Vec width matches cluster's rocc.cmd/rocc.resp Vec width); per-core wire-up correctly uses numCores. PHY instances are tied off using the v1 behavioral PHY contract from PR #116 (tx.data zeros, phyResetReq/trainReq false, berDenominator/dropEvery zero). Fabric CSR / credits are tied off with documented "TBD per ADR-008 — eFuse / tie-off" for myChipId and "Open question on creditReturn protocol" annotation. Cluster clusterStop held inactive with the right reason ("chip-level CSR sequencing is Open per SPEC §Behavior"). Tests verify both Issue #125 scenarios cleanly using Scala-level Option[PCIeHostBridge] introspection: FluidPopMasterConfig → c.pcie.isDefined, FluidPopSlaveConfig → c.pcie.isEmpty, plus an assertion on the corresponding IsMasterKey resolution. The default constructor uses FluidPopMasterConfig so the legacy should "elaborate" smoke test still works. The data-path attaches (cluster ↔ fabric ↔ PHY) are honestly deferred with explicit forward-links to the sibling SPECs' Open questions — the fabric phy bundle stays empty, the cluster popLink/mem/perfCounters subbundles drive DontCare internally, and no concrete bundle shapes are invented at this v1.

Findings

None.

**VERDICT:** PASS PR #130 lifts `FluidPopSoC` from elaborate-only into the v1 end-to-end wire-up that ties together all the v1 submodules landed in prior PRs (#107 PopRoCCRouter, #114→#126 MultiGemminiCluster, #127 InterChipFabric, #116 PopLinkPHY_Behavioral, #94→ PCIeHostBridge), scoped cleanly to Issue #125. Mechanical guardrails pass: SPDX headers preserved (`CHARRUA-1.2` source, `AGPL-3.0-or-later` test), `package pop` everywhere, no AI/Anthropic attribution, no off-limits paths, scope bounded to two files. Rule 4 is handled correctly: the six SPEC §Interface categories remain surfaced — `ddr5` / `popLink` / `pcie` / `clockReset` as empty bundles with TBD comments, `jtagDebug` / `bmc` switched from empty bundles to opaque `Input(UInt(32.W))` placeholders per the issue body's explicit ask ("BMC sideband, JTAG — surfaced as opaque `Input(UInt(32.W))` placeholders, annotated"). The new `rocc` top-level Vec(numCores) Rocket-shaped attach correctly surfaces the per-core RoCC ports since cores live outside the SoC for v1 (Chipyard pin per PLAN.md §6 Week 4 still pending). Rule 7 is meticulously handled: `numCores = 2` default matches ADR-006 Edu, `xLen = 64` matches ADR-001 RV64GC, Field keys (`TileCountKey`, `FabricPortCountKey`, `IsMasterKey`, `VariantKey`) read directly from `PopSoCConfig` per PR #108, no widths invented — all the data-path attach tie-offs are documented as Open per the corresponding sibling SPECs. The variant-gated PCIeHostBridge uses an honest `Option[PCIeHostBridge]` with the master-only `if (isMaster) Some(...) else None` pattern matching ADR-008 Decision verbatim. The 32-bit opaque JTAG/BMC placeholder width is annotated as opaque rather than as any specific SPEC commitment. Per-tile wire-up correctly uses `tileCount` (router's `tileCmd`/`tileResp` Vec width matches cluster's `rocc.cmd`/`rocc.resp` Vec width); per-core wire-up correctly uses `numCores`. PHY instances are tied off using the v1 behavioral PHY contract from PR #116 (`tx.data` zeros, `phyResetReq`/`trainReq` false, `berDenominator`/`dropEvery` zero). Fabric CSR / credits are tied off with documented "TBD per ADR-008 — eFuse / tie-off" for `myChipId` and "Open question on creditReturn protocol" annotation. Cluster `clusterStop` held inactive with the right reason ("chip-level CSR sequencing is Open per SPEC §Behavior"). Tests verify both Issue #125 scenarios cleanly using Scala-level `Option[PCIeHostBridge]` introspection: `FluidPopMasterConfig` → `c.pcie.isDefined`, `FluidPopSlaveConfig` → `c.pcie.isEmpty`, plus an assertion on the corresponding `IsMasterKey` resolution. The default constructor uses `FluidPopMasterConfig` so the legacy `should "elaborate"` smoke test still works. The data-path attaches (cluster ↔ fabric ↔ PHY) are honestly deferred with explicit forward-links to the sibling SPECs' Open questions — the fabric `phy` bundle stays empty, the cluster `popLink`/`mem`/`perfCounters` subbundles drive `DontCare` internally, and no concrete bundle shapes are invented at this v1. ## Findings _None._

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