rtl: PCIeHostBridge skeleton + chiseltest elaborate bench #65

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navigator merged 1 commit from auto/issue-50-20260525T201137Z_issue50 into main

2026-05-25 17:18:32 -03:00

navigator commented

2026-05-25 17:17:35 -03:00

Owner

Implements the Chisel skeleton + chiseltest elaborate bench for
PCIeHostBridge per rtl/src/pop/specs/PCIeHostBridge.SPEC.md.

What this PR lands

rtl/src/pop/PCIeHostBridge.scala — skeleton module. IO bundle
groups the four bullets from SPEC §Interface (pipe, hostTlp,
fabric, msix) as empty sub-bundles, each annotated with
// TBD per SPEC §Interface. Module ties everything to DontCare.
No widths or timing invented. SPDX: CHARRUA-1.2.
rtl/tests/PCIeHostBridge/PCIeHostBridgeSpec.scala — chiseltest
AnyFlatSpec with one should "elaborate" case. SPDX: AGPL-3.0-or-later.
rtl/build.sbt + rtl/project/build.properties — standalone sbt
build pinned to Chipyard 1.13.0 versions (Scala 2.13.12, Chisel
6.5.0, chiseltest 6.0.0). sbt runner pinned to 1.10.7 because
Chipyard's 1.8.2 can't parse JDK 21 class files on the agent host.
rtl/README.md — updated to reflect the new build.
.gitignore — adds test_run_dir/ (chiseltest scratch).

Acceptance criteria (issue #50)

rtl/src/pop/PCIeHostBridge.scala exists, sbt compile green
IO bundle reflects SPEC §Interface (empty sub-bundles + TBD comments)
N/A — module is a leaf, no parent wiring this round
rtl/tests/PCIeHostBridge/PCIeHostBridgeSpec.scala with should "elaborate"
SPDX: CHARRUA-1.2 on source, AGPL-3.0-or-later on test
No fabricated TBD values

Local validation

$ cd rtl && sbt -batch compile
[success] Total time: 6 s

$ sbt -batch test
[info] PCIeHostBridgeSpec:
[info] PCIeHostBridge
[info] - should elaborate
[info] Tests: succeeded 1, failed 0
[success] Total time: 7 s

Closes #50.

Implements the Chisel skeleton + chiseltest elaborate bench for `PCIeHostBridge` per `rtl/src/pop/specs/PCIeHostBridge.SPEC.md`. ## What this PR lands - `rtl/src/pop/PCIeHostBridge.scala` — skeleton module. IO bundle groups the four bullets from SPEC §Interface (`pipe`, `hostTlp`, `fabric`, `msix`) as empty sub-bundles, each annotated with `// TBD per SPEC §Interface`. Module ties everything to `DontCare`. No widths or timing invented. SPDX: CHARRUA-1.2. - `rtl/tests/PCIeHostBridge/PCIeHostBridgeSpec.scala` — chiseltest `AnyFlatSpec` with one `should "elaborate"` case. SPDX: AGPL-3.0-or-later. - `rtl/build.sbt` + `rtl/project/build.properties` — standalone sbt build pinned to Chipyard 1.13.0 versions (Scala 2.13.12, Chisel 6.5.0, chiseltest 6.0.0). sbt runner pinned to 1.10.7 because Chipyard's 1.8.2 can't parse JDK 21 class files on the agent host. - `rtl/README.md` — updated to reflect the new build. - `.gitignore` — adds `test_run_dir/` (chiseltest scratch). ## Acceptance criteria (issue #50) - [x] `rtl/src/pop/PCIeHostBridge.scala` exists, `sbt compile` green - [x] IO bundle reflects SPEC §Interface (empty sub-bundles + TBD comments) - [x] N/A — module is a leaf, no parent wiring this round - [x] `rtl/tests/PCIeHostBridge/PCIeHostBridgeSpec.scala` with `should "elaborate"` - [x] SPDX: CHARRUA-1.2 on source, AGPL-3.0-or-later on test - [x] No fabricated TBD values ## Local validation ``` $ cd rtl && sbt -batch compile [success] Total time: 6 s $ sbt -batch test [info] PCIeHostBridgeSpec: [info] PCIeHostBridge [info] - should elaborate [info] Tests: succeeded 1, failed 0 [success] Total time: 7 s ``` Closes #50.

navigator added 1 commit

2026-05-25 17:17:36 -03:00

rtl: PCIeHostBridge skeleton + chiseltest elaborate bench

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174d93bfad

Lands the buildable Scala skeleton for the master-only PCIe Gen4 x16
bridge module per rtl/src/pop/specs/PCIeHostBridge.SPEC.md. Skeleton
only: IO bundle groups the four §Interface bullets (pipe, hostTlp,
fabric, msix) as empty sub-bundles with `// TBD per SPEC §Interface`
annotations -- no widths or timing are invented. Module ties all sub-
bundles to DontCare.

Adds a standalone rtl/build.sbt pinned to the same versions as
Chipyard 1.13.0 (Scala 2.13.12, Chisel 6.5.0, chiseltest 6.0.0) so
the tree compiles with plain `sbt compile` without needing a Chipyard
checkout, while staying source-compatible for later integration.
sbt runner pinned to 1.10.7 because Chipyard's 1.8.2 cannot parse
JDK 21 class files (the agent host JDK).

The chiseltest bench under rtl/tests/PCIeHostBridge/ exercises the
PLAN.md §12.3 elaborate floor only -- one `should "elaborate"` case.
Behavior, MSI-X/doorbell, ATU programming, ordering checks, and the
coverage targets (≥85%/70% line/cond at Phase-3 close; ≥95%/85% at
sign-off) come in follow-up issues.

Closes #50.