spec(PCIeHostBridge): promote PCIeHostBridge.SPEC.md to Draft #94

Merged

navigator merged 1 commit from spec/pciehostbridge-draft into main 2026-05-26 02:10:45 -03:00

Conversation 2 Commits 1 Files changed 1 +36 -6

navigator commented 2026-05-26 02:09:02 -03:00

Owner

Copy link

Refs #50 (companion Chisel skeleton, area:rtl, closed via #65).
Refs #80 (spec-designer role onboarding).

This PR is opened by the autonomous spec-designer role; per
infra/ops/agents/roles/spec-designer.sh the role is designer-driven
and runs without a dedicated source issue, so no Closes # is attached.
If the swarm policy requires a tracking issue per promotion, the
follow-up tweak belongs in the role script, not in this SPEC change.

Summary

Promotes rtl/src/pop/specs/PCIeHostBridge.SPEC.md from
Status: Stub to Status: Draft. No behaviour, no Chisel, no
edits outside the single SPEC file. The IO contract is pinned to ADRs
and to sibling SPECs already in Draft (FluidPopSoC,
InterChipFabric); widths and signal sets that no source pins are
recorded as _Open question:_ rather than invented.

Resolved TBDs

• §Interface — Gen4 x16 PIPE-style attach (vendor PHY): master-only
  presence pinned to ADR-008 Decision ("in master mode the PCIe x16
  endpoint is enabled, in slave mode it is gated"). Host-attach
  exclusivity pinned to ADR-009 Decision ("PCIe Gen4 x16 retained only
  on master chip for host-to-board connection"). Ball-budget envelope
  ~80 PCIe balls (Edu preliminary) pinned to ADR-014 Decision via the
  parent SPEC rtl/src/pop/specs/FluidPopSoC.SPEC.md §Interface.
• §Interface — chip-side memory-mapped fabric port: cross-chip
  transaction set pinned to PLAN.md §3.6 ("REMOTE_READ_REQ/RESP,
  REMOTE_WRITE, REMOTE_WRITE_ACK, ATOMIC_OP/RESP, DMA_DESC,
  DMA_COMPLETE, BARRIER_ARRIVE/RELEASE, DOORBELL, BROADCAST, MGMT")
  via the sibling Draft rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface. Cross-chip memory model pinned to ADR-011 Decision
  ("Cross-chip data movement is explicit via PopLink transactions").
• §Behavior — BAR / ATU programming: purpose framed against
  ADR-009 Decision (PopLink as inter-chip protocol). Specific BAR /
  ATU counts and granularity recorded as Open.
• §Behavior — DMA descriptor processing: on-fabric encoding for
  remote-SoC DMA pinned to the PLAN.md §3.6 DMA_DESC /
  DMA_COMPLETE packet types via the sibling Draft InterChipFabric.
• §Behavior — Cross-SoC address translation onto PopLink: fully
  pinned to ADR-009 Decision (PopLink as inter-chip protocol),
  ADR-008 Decision (single-master rule), PLAN.md §3.6 transaction set
  via the sibling Draft, and ADR-011 Decision (non-coherent
  cross-chip).
• §Behavior — Host interrupt aggregation: fabric-side escalation
  path pinned to the sibling Draft rtl/src/pop/specs/InterChipFabric.SPEC.md §Behavior (ARQ / link-error escalation surface).
• §Invariants — PCIe ordering rules honoured: preserved verbatim
  from the Stub with the PCIe 5.0 §2.4 (Transaction Ordering)
  reference the Stub already names.
• §Invariants — No host-visible stall longer than spec timeout:
  preserved verbatim from the Stub.
• §Invariants — No fabric→host TLP without matching request:
  preserved verbatim from the Stub.
• §Invariants — Master-only instantiation: pinned to ADR-008
  Decision and ADR-008 Consequences ("All 8 chips share one mask set
  (cheaper tapeout)"). Variant selection at elaboration time via
  FluidPopMasterConfig / FluidPopSlaveConfig per PLAN.md §8.2
  via the parent SPEC rtl/src/pop/specs/FluidPopSoC.SPEC.md §Behavior.
• §Invariants — Single host attach on a board: derived from
  ADR-009 Decision and the ADR-008 single-master rule, cross-checked
  against the parent SPEC rtl/src/pop/specs/FluidPopSoC.SPEC.md §Invariants single-master invariant.
• §Invariants — Non-coherent semantics preserved across fabric
  exit: pinned to the explicit transaction set of PLAN.md §3.6
  via the sibling Draft rtl/src/pop/specs/InterChipFabric.SPEC.md §Invariants plus ADR-011 Decision software contract ("Software
  responsibility to partition workloads and orchestrate data
  movement").

Open questions (recorded as _Open question:_ in the SPEC)

• PIPE PCS sideband signal set and per-lane SerDes data-width
  (lane / line-rate triple) — pending PCIe PHY vendor-selection ADR;
  the parent SPEC FluidPopSoC.SPEC.md §Interface explicitly defers
  this surface to this SPEC.
• Chip-side TLP request / completion bundle shape (header width,
  data-bus width, completion-credit accounting) — pending PHY
  selection.
• Chip-side fabric-port bundle shape (request / response port count
  toward InterChipFabric, request-ID width, in-flight tracking
  depth) — mirrors the same Open question on the sibling Draft
  InterChipFabric.SPEC.md §Interface; resolves jointly once one
  side commits a concrete attach shape.
• MSI-X vector count, vector-table address map, per-source doorbell
  layout, and host-interrupt aggregation policy — pending
  interrupt-policy ADR.
• BAR count, per-BAR size, ATU window count, and ATU translation
  granularity — pending host-driver IOCTL commit.
• DMA descriptor format (chain layout, completion-status encoding,
  scatter-gather entry count) — pending host-driver commit.
• Host-side address-to-remote-chip mapping (single linear
  board-physical aperture vs per-chip BARs) — pending host-driver
  ADR.
• Aggregation policy (per-source vector vs grouped vector,
  coalescing window, level-vs-edge semantics) — pending
  interrupt-policy ADR.

Constraint check

• **Status:** line flipped Stub → Draft.
• Every TBD resolved (pin to ADR / PLAN / sibling Draft, or
  recorded as _Open question:_). No fabricated widths or signal
  sets.
• Only rtl/src/pop/specs/PCIeHostBridge.SPEC.md changes
  (ADR-017 off-limits path policy honoured).
• All ADR / PLAN refs from the Stub preserved (PLAN.md §8.2,
  §12.3, ADR-008, ADR-009). Draft body cites additional refs the
  body relies on for pins (PLAN.md §3.6, §12.5, §12.7, ADR-011,
  ADR-014) — added refs only, none removed.
• Sibling Drafts cited as pins only when actually in Draft
  (FluidPopSoC, InterChipFabric). Stub siblings
  (PopLinkPHY_Behavioral, PopRoCCRouter, PopSoCConfig) are
  not used as Draft-pin sources.
• ## Promotion history appended with the 2026-05-26 entry.
• No fabricated performance / latency / capacity / vendor
  commitments — every number quoted has an ADR title or Decision
  as source.

Refs #50 (companion Chisel skeleton, area:rtl, closed via #65). Refs #80 (spec-designer role onboarding). This PR is opened by the autonomous `spec-designer` role; per `infra/ops/agents/roles/spec-designer.sh` the role is designer-driven and runs without a dedicated source issue, so no `Closes #` is attached. If the swarm policy requires a tracking issue per promotion, the follow-up tweak belongs in the role script, not in this SPEC change. ## Summary Promotes `rtl/src/pop/specs/PCIeHostBridge.SPEC.md` from **Status: Stub** to **Status: Draft**. No behaviour, no Chisel, no edits outside the single SPEC file. The IO contract is pinned to ADRs and to sibling SPECs already in Draft (`FluidPopSoC`, `InterChipFabric`); widths and signal sets that no source pins are recorded as `_Open question:_` rather than invented. ## Resolved TBDs - **§Interface — Gen4 x16 PIPE-style attach (vendor PHY)**: master-only presence pinned to ADR-008 Decision ("in master mode the PCIe x16 endpoint is enabled, in slave mode it is gated"). Host-attach exclusivity pinned to ADR-009 Decision ("PCIe Gen4 x16 retained only on master chip for host-to-board connection"). Ball-budget envelope ~80 PCIe balls (Edu preliminary) pinned to ADR-014 Decision via the parent SPEC `rtl/src/pop/specs/FluidPopSoC.SPEC.md §Interface`. - **§Interface — chip-side memory-mapped fabric port**: cross-chip transaction set pinned to PLAN.md §3.6 ("REMOTE_READ_REQ/RESP, REMOTE_WRITE, REMOTE_WRITE_ACK, ATOMIC_OP/RESP, DMA_DESC, DMA_COMPLETE, BARRIER_ARRIVE/RELEASE, DOORBELL, BROADCAST, MGMT") via the sibling Draft `rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface`. Cross-chip memory model pinned to ADR-011 Decision ("Cross-chip data movement is explicit via PopLink transactions"). - **§Behavior — BAR / ATU programming**: purpose framed against ADR-009 Decision (PopLink as inter-chip protocol). Specific BAR / ATU counts and granularity recorded as Open. - **§Behavior — DMA descriptor processing**: on-fabric encoding for remote-SoC DMA pinned to the PLAN.md §3.6 `DMA_DESC` / `DMA_COMPLETE` packet types via the sibling Draft `InterChipFabric`. - **§Behavior — Cross-SoC address translation onto PopLink**: fully pinned to ADR-009 Decision (PopLink as inter-chip protocol), ADR-008 Decision (single-master rule), PLAN.md §3.6 transaction set via the sibling Draft, and ADR-011 Decision (non-coherent cross-chip). - **§Behavior — Host interrupt aggregation**: fabric-side escalation path pinned to the sibling Draft `rtl/src/pop/specs/InterChipFabric.SPEC.md §Behavior` (ARQ / link-error escalation surface). - **§Invariants — PCIe ordering rules honoured**: preserved verbatim from the Stub with the PCIe 5.0 §2.4 (Transaction Ordering) reference the Stub already names. - **§Invariants — No host-visible stall longer than spec timeout**: preserved verbatim from the Stub. - **§Invariants — No fabric→host TLP without matching request**: preserved verbatim from the Stub. - **§Invariants — Master-only instantiation**: pinned to ADR-008 Decision and ADR-008 Consequences ("All 8 chips share one mask set (cheaper tapeout)"). Variant selection at elaboration time via `FluidPopMasterConfig` / `FluidPopSlaveConfig` per PLAN.md §8.2 via the parent SPEC `rtl/src/pop/specs/FluidPopSoC.SPEC.md §Behavior`. - **§Invariants — Single host attach on a board**: derived from ADR-009 Decision and the ADR-008 single-master rule, cross-checked against the parent SPEC `rtl/src/pop/specs/FluidPopSoC.SPEC.md §Invariants` single-master invariant. - **§Invariants — Non-coherent semantics preserved across fabric exit**: pinned to the explicit transaction set of PLAN.md §3.6 via the sibling Draft `rtl/src/pop/specs/InterChipFabric.SPEC.md §Invariants` plus ADR-011 Decision software contract ("Software responsibility to partition workloads and orchestrate data movement"). ## Open questions (recorded as `_Open question:_` in the SPEC) - PIPE PCS sideband signal set and per-lane SerDes data-width (lane / line-rate triple) — pending PCIe PHY vendor-selection ADR; the parent SPEC `FluidPopSoC.SPEC.md §Interface` explicitly defers this surface to this SPEC. - Chip-side TLP request / completion bundle shape (header width, data-bus width, completion-credit accounting) — pending PHY selection. - Chip-side fabric-port bundle shape (request / response port count toward `InterChipFabric`, request-ID width, in-flight tracking depth) — mirrors the same Open question on the sibling Draft `InterChipFabric.SPEC.md §Interface`; resolves jointly once one side commits a concrete attach shape. - MSI-X vector count, vector-table address map, per-source doorbell layout, and host-interrupt aggregation policy — pending interrupt-policy ADR. - BAR count, per-BAR size, ATU window count, and ATU translation granularity — pending host-driver IOCTL commit. - DMA descriptor format (chain layout, completion-status encoding, scatter-gather entry count) — pending host-driver commit. - Host-side address-to-remote-chip mapping (single linear board-physical aperture vs per-chip BARs) — pending host-driver ADR. - Aggregation policy (per-source vector vs grouped vector, coalescing window, level-vs-edge semantics) — pending interrupt-policy ADR. ## Constraint check - [x] `**Status:**` line flipped Stub → Draft. - [x] Every TBD resolved (pin to ADR / PLAN / sibling Draft, or recorded as `_Open question:_`). No fabricated widths or signal sets. - [x] Only `rtl/src/pop/specs/PCIeHostBridge.SPEC.md` changes (ADR-017 off-limits path policy honoured). - [x] All ADR / PLAN refs from the Stub preserved (PLAN.md §8.2, §12.3, ADR-008, ADR-009). Draft body cites additional refs the body relies on for pins (PLAN.md §3.6, §12.5, §12.7, ADR-011, ADR-014) — added refs only, none removed. - [x] Sibling Drafts cited as pins only when actually in Draft (`FluidPopSoC`, `InterChipFabric`). Stub siblings (`PopLinkPHY_Behavioral`, `PopRoCCRouter`, `PopSoCConfig`) are not used as Draft-pin sources. - [x] `## Promotion history` appended with the 2026-05-26 entry. - [x] No fabricated performance / latency / capacity / vendor commitments — every number quoted has an ADR title or Decision as source.

navigator added 1 commit 2026-05-26 02:09:02 -03:00

spec(PCIeHostBridge): promote PCIeHostBridge.SPEC.md to Draft ... 360ed02049

Promotes rtl/src/pop/specs/PCIeHostBridge.SPEC.md from Status: Stub to
Status: Draft. No behaviour, no Chisel, no edits outside the single SPEC
file. The IO contract is pinned to ADRs and to sibling SPECs already in
Draft (FluidPopSoC, InterChipFabric); widths and signal sets that no
source pins are recorded as _Open question:_ rather than invented.

Resolved TBDs:
- §Interface — Gen4 x16 PIPE-style attach: master-only presence pinned
  to ADR-008 Decision; host-attach exclusivity pinned to ADR-009
  Decision; ball-budget envelope (~80 PCIe balls Edu preliminary)
  pinned to ADR-014 Decision via the parent SPEC FluidPopSoC.SPEC.md
  §Interface.
- §Interface — chip-side memory-mapped fabric port: cross-chip
  transaction set pinned to PLAN.md §3.6 via the sibling Draft
  InterChipFabric.SPEC.md §Interface; cross-chip memory model pinned
  to ADR-011 Decision.
- §Behavior — cross-SoC address translation onto PopLink: fully pinned
  to ADR-009 Decision (PopLink as inter-chip protocol; PCIe Gen4 x16
  retained only on master chip), ADR-008 Decision (single-master
  rule), and PLAN.md §3.6 transaction set via the sibling Draft.
- §Behavior — host interrupt aggregation: fabric-side escalation path
  pinned to the sibling Draft InterChipFabric.SPEC.md §Behavior.
- §Invariants — PCIe ordering / no-stall / no-unsolicited-TLP:
  preserved verbatim from the Stub with the PCIe 5.0 §2.4 reference
  the Stub already names.
- §Invariants — master-only instantiation: pinned to ADR-008 Decision
  and ADR-008 Consequences; variant selection pinned to PLAN.md §8.2
  Config-fragment names via the parent SPEC FluidPopSoC.SPEC.md
  §Behavior.
- §Invariants — single host attach on a board: derived from ADR-009
  Decision + ADR-008 single-master rule and the parent SPEC
  FluidPopSoC.SPEC.md §Invariants.
- §Invariants — non-coherent semantics across fabric exit: pinned to
  PLAN.md §3.6 explicit transaction set (via the sibling Draft
  InterChipFabric.SPEC.md §Invariants) and ADR-011 Decision.

Open questions (recorded as _Open question:_ in the SPEC):
- PIPE PCS sideband signal set and per-lane SerDes data-width
  (lane / line-rate triple) — pending PCIe PHY vendor-selection.
- Chip-side TLP request / completion bundle shape — pending PHY
  selection and host-driver shape.
- Chip-side fabric-port bundle shape — mirrors the Open question on
  the sibling Draft InterChipFabric.SPEC.md §Interface; resolves
  jointly.
- MSI-X vector count, vector-table address map, doorbell layout,
  and host-interrupt aggregation policy — pending interrupt-policy
  ADR.
- BAR count, per-BAR size, ATU window count, and ATU translation
  granularity — pending host-driver IOCTL commit.
- DMA descriptor format (chain layout, completion-status encoding,
  scatter-gather entry count) — pending host-driver commit.
- Host-side address-to-remote-chip mapping (single linear aperture
  vs per-chip BARs) — pending host-driver ADR.
- Aggregation policy (per-source vs grouped vector, coalescing
  window, level-vs-edge) — pending interrupt-policy ADR.

Constraint check:
- **Status:** line flipped Stub -> Draft.
- Every TBD resolved (pin to ADR / PLAN / sibling Draft, or recorded
  as _Open question:_). No fabricated widths or signal sets.
- Only rtl/src/pop/specs/PCIeHostBridge.SPEC.md changes (ADR-017
  off-limits path policy honoured).
- All ADR / PLAN refs from the Stub preserved (PLAN.md §8.2, §12.3,
  ADR-008, ADR-009). Draft body cites additional refs the body relies
  on for pins (PLAN.md §3.6, §12.5, §12.7, ADR-011, ADR-014) — added
  refs only, none removed.
- Sibling Drafts cited as pins only when actually in Draft
  (FluidPopSoC, InterChipFabric).
- ## Promotion history appended with the 2026-05-26 entry.
- No fabricated performance / latency / capacity / vendor
  commitments.

navigator added the

ready-for-review

label 2026-05-26 02:09:11 -03:00

navigator commented 2026-05-26 02:09:55 -03:00

Author

Owner

Copy link

VERDICT: PASS

PR #94 promotes rtl/src/pop/specs/PCIeHostBridge.SPEC.md from Stub to Draft following the same disciplined pattern as PR #87, PR #91, PR #92, and PR #93. Mechanical guardrails pass: existing SPDX header preserved (diff starts at line 4), single file touched, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply, autonomous spec-designer role explains missing Closes #. Rule 7 is the critical one and the PR is meticulous: every concrete claim is a verbatim quote from an ADR Decision/Consequences or a PLAN.md section, with the source pinned inline. Cross-checking against approved PRs in this thread: ADR-008 Decision quote ("SoC 0 = identical mask set with eFuse / tie-off bit selecting master mode; in master mode the PCIe x16 endpoint is enabled, in slave mode it is gated") and Consequences ("All 8 chips share one mask set (cheaper tapeout)") match PR #87 verbatim; ADR-009 Decision ("Adopt PopLink as the inter-chip protocol (4 layers: PHY/Link/Routing/Transaction)" + "PCIe Gen4 x16 retained only on master chip for host-to-board connection") matches PR #91; ADR-011 Decision ("Cross-chip data movement is explicit via PopLink transactions" + software-responsibility consequence) matches PR #87/#91/#92/#93; PLAN.md §3.6 transaction set ("REMOTE_READ_REQ/RESP, REMOTE_WRITE, REMOTE_WRITE_ACK, ATOMIC_OP/RESP, DMA_DESC, DMA_COMPLETE, BARRIER_ARRIVE/RELEASE, DOORBELL, BROADCAST, MGMT") matches PR #91/#93; ADR-014's ~80 PCIe-ball envelope matches PR #87. PCIe-specific facts that could tempt fabrication (BAR count, per-BAR size, ATU window count and granularity, MSI-X vector count, DMA descriptor format, lane/line-rate triple, host-side aperture mapping, interrupt-aggregation policy) are all honestly parked as Open Questions tied to pending ADRs (PCIe PHY vendor selection, host-driver IOCTL commit, interrupt-policy ADR) rather than invented. PCIe-spec invariants preserved from the Stub (PCIe 5.0 §2.4 transaction ordering, completion-timeout window, no unsolicited fabric→host TLP) are framed as hard correctness contracts at the host boundary rather than redefined. Sibling Draft references (FluidPopSoC §Interface/§Behavior/§Invariants, InterChipFabric §Interface/§Behavior/§Invariants) cite SPECs that are in fact Draft per PR #87 and PR #91, exactly as the constraint check states; Stub-status siblings (PopLinkPHY_Behavioral, PopRoCCRouter, PopSoCConfig) are not used as Draft-pin sources. The chip-side fabric-port "Open question" honestly mirrors the same shape recorded as Open on InterChipFabric's side, with explicit text saying it "resolves jointly once one of the two SPECs commits a concrete attach shape" — that's the right way to handle paired Open questions across sibling SPECs. Promotion history entry is appropriate.

Findings

None.

<!-- agent:review verdict=PASS ts=1779772194 --> **VERDICT:** PASS PR #94 promotes `rtl/src/pop/specs/PCIeHostBridge.SPEC.md` from Stub to Draft following the same disciplined pattern as PR #87, PR #91, PR #92, and PR #93. Mechanical guardrails pass: existing SPDX header preserved (diff starts at line 4), single file touched, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply, autonomous `spec-designer` role explains missing `Closes #`. Rule 7 is the critical one and the PR is meticulous: every concrete claim is a verbatim quote from an ADR Decision/Consequences or a PLAN.md section, with the source pinned inline. Cross-checking against approved PRs in this thread: ADR-008 Decision quote ("SoC 0 = identical mask set with eFuse / tie-off bit selecting master mode; in master mode the PCIe x16 endpoint is enabled, in slave mode it is gated") and Consequences ("All 8 chips share one mask set (cheaper tapeout)") match PR #87 verbatim; ADR-009 Decision ("Adopt PopLink as the inter-chip protocol (4 layers: PHY/Link/Routing/Transaction)" + "PCIe Gen4 x16 retained only on master chip for host-to-board connection") matches PR #91; ADR-011 Decision ("Cross-chip data movement is explicit via PopLink transactions" + software-responsibility consequence) matches PR #87/#91/#92/#93; PLAN.md §3.6 transaction set ("REMOTE_READ_REQ/RESP, REMOTE_WRITE, REMOTE_WRITE_ACK, ATOMIC_OP/RESP, DMA_DESC, DMA_COMPLETE, BARRIER_ARRIVE/RELEASE, DOORBELL, BROADCAST, MGMT") matches PR #91/#93; ADR-014's ~80 PCIe-ball envelope matches PR #87. PCIe-specific facts that *could* tempt fabrication (BAR count, per-BAR size, ATU window count and granularity, MSI-X vector count, DMA descriptor format, lane/line-rate triple, host-side aperture mapping, interrupt-aggregation policy) are all honestly parked as Open Questions tied to pending ADRs (PCIe PHY vendor selection, host-driver IOCTL commit, interrupt-policy ADR) rather than invented. PCIe-spec invariants preserved from the Stub (PCIe 5.0 §2.4 transaction ordering, completion-timeout window, no unsolicited fabric→host TLP) are framed as hard correctness contracts at the host boundary rather than redefined. Sibling Draft references (FluidPopSoC §Interface/§Behavior/§Invariants, InterChipFabric §Interface/§Behavior/§Invariants) cite SPECs that are in fact Draft per PR #87 and PR #91, exactly as the constraint check states; Stub-status siblings (PopLinkPHY_Behavioral, PopRoCCRouter, PopSoCConfig) are not used as Draft-pin sources. The chip-side fabric-port "Open question" honestly mirrors the same shape recorded as Open on InterChipFabric's side, with explicit text saying it "resolves jointly once one of the two SPECs commits a concrete attach shape" — that's the right way to handle paired Open questions across sibling SPECs. Promotion history entry is appropriate. ## Findings _None._

navigator added the

review:pass

label 2026-05-26 02:09:55 -03:00

fluidpop-bot approved these changes 2026-05-26 02:10:43 -03:00

fluidpop-bot left a comment

Collaborator

Copy link

CI green (head 360ed02049), auto-approving

CI green (head 360ed02049d10468e0fad178d8dcf9d47482c385), auto-approving

navigator merged commit 5ebedf4ed8 into main 2026-05-26 02:10:45 -03:00

navigator referenced this pull request from a commit 2026-05-26 02:10:46 -03:00

spec(PCIeHostBridge): promote PCIeHostBridge.SPEC.md to Draft (#94)

navigator referenced this pull request 2026-05-26 02:26:28 -03:00

spec(PopLinkPHY_Behavioral): promote PopLinkPHY_Behavioral.SPEC.md to Draft #95

navigator referenced this pull request 2026-05-26 02:43:17 -03:00

spec(PopRoCCRouter): promote PopRoCCRouter.SPEC.md to Draft #96

navigator referenced this pull request 2026-05-26 02:59:54 -03:00

spec(PopSoCConfig): promote PopSoCConfig.SPEC.md to Draft #97

Sign in to join this conversation.

Reviewers

No reviewers

fluidpop-bot

Labels

Clear labels   

adr

Architecture Decision Record

  

agent:blocked-ci

CI failed on the PR

  

agent:blocked-human

Operator escalated; awaiting Marcos input

  

agent:blocked-resolver

Resolver crashed, returned empty, or timed out

  

agent:done

PR merged; issue auto-closed

  

agent:in-progress

Resolver claimed and running

  

agent:no-touch

Human-reserved; swarm Opener/Dispatcher skip

  

agent:pinged

Operator already escalated; suppress repeat pings

  

agent:pr-open

Resolver opened a PR; awaiting review/merge

  

agent:queued

Issue ready for swarm Resolver to claim

  

agent:wip

PR work-in-progress; Approver skips

  

area:board

PCB / mechanical / cooling

  

area:funding

PACID / grants / RFQs

  

area:infra

Dev env, CI, containers

  

area:phy

Physical layer / SerDes

  

area:poplink

PopLink protocol

  

area:rtl

Chisel/RTL work

  

area:software

Driver / runtime / frameworks

  

area:supply-chain

Foundry, OSAT, PCB, components

  

area:verification

Test, formal, coverage

  

ci-failed

auto-merge.sh detected CI failure

  

ci-timeout

auto-merge.sh hit CI timeout

  

docs

Documentation

  

do-not-merge

Hard hold; PR Approver skips

  

human-approved

Marcos approved via Telegram; release governance hold

  

needs-human-approval

Touches governance path; awaits Marcos label human-approved

  

needs-rebase

PR is not mergeable; rebase needed

  

needs-triage

Issue from untrusted author; Marcos triage needed

  

phase:1

Phase 1 (Section 6 of PLAN.md)

  

ready-for-review

Resolver done; PR Approver triages

  

review:findings

PR semantic review flagged blocking findings

  

review:pass

PR semantic review passed; safe for pr-approver

  

risk:tripwire

Section 0.5 tripwire fired

  

swarm:quarantined

Escalation tripwire fired; resolver tried off-limits paths

No labels

adr

agent:blocked-ci

agent:blocked-human

agent:blocked-resolver

agent:done

agent:in-progress

agent:no-touch

agent:pinged

agent:pr-open

agent:queued

agent:wip

area:board

area:funding

area:infra

area:phy

area:poplink

area:rtl

area:software

area:supply-chain

area:verification

ci-failed

ci-timeout

docs

do-not-merge

human-approved

needs-human-approval

needs-rebase

needs-triage

phase:1

ready-for-review

review:findings

review:pass

risk:tripwire

swarm:quarantined

Milestone

Clear milestone

No items

No milestone

Projects

Clear projects

No items

No project

Assignees

Clear assignees

No assignees

2 participants

Notifications

Subscribe

Due date

The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference

Fluid/fluidpop-v1!94

No description provided.