Draft docs/spec/pop-accel-8-board-v1.md board spec skeleton #85

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opened 2026-05-26 00:55:59 -03:00 by navigator · 2 comments

navigator commented

2026-05-26 00:55:59 -03:00

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Goal

Create the board spec skeleton at docs/spec/pop-accel-8-board-v1.md, listed as deliverable #2 in PLAN.md Section 10. The doc gathers board-level decisions (ADR-008 through ADR-014) so PCB, cooling, supply-chain, and funding work share a single board reference.

Sections to include:

Overview (FluidPopV1 production board: 8 SoCs in 2x4 torus per ADR-010, designated master per ADR-008)
Form factor (OAM 2.0 per ADR-013)
Inter-chip fabric (PopLink 2D torus per ADR-009/010; non-coherent memory per ADR-011)
Memory subsystem (8 DDR5 RDIMMs, one per SoC per ADR-005)
Host interface (PCIe Gen4 x16 via master SoC only)
Power and thermal (per-chip 50 W typ / 70 W max per ADR-012; board-level budget ~400-560 W; cold-plate cooling per Section 15.11)
Stack-up and signal integrity (14-16 layer impedance-controlled, Megtron 6+ per Section 15.4)
BMC subsystem (WCH CH32V307 candidate per Section 15.8)
Connectors (Luxshare-ICT OAM-qualified per Section 15.9)
Assembly requirements (FC-BGA >1500 balls, X-ray / ball-shear / CSAM per Section 15.5)
Open questions (clock distribution, JTAG topology, telemetry side-band)

Acceptance criteria

docs/spec/pop-accel-8-board-v1.md exists with the sections above
Status: Draft skeleton + Owner: TBD header
Each section has TODO markers and 2-3 line intent description
References ADR placeholders 008-014 explicitly
No fabricated dimensions or trace impedance numbers — only values already in PLAN.md
Cross-references PLAN.md Sections 10, 8.1 (board-level ADRs), 15.4/15.5/15.8/15.9/15.11

Plan refs

Section 10 (deliverable #2), Section 8.1 (board-level ADRs), Section 11.2.B (production board cost frame), Sections 15.4/15.5/15.8/15.9/15.11 (supplier inputs)

Notes

Skeleton only — final mechanical/electrical numbers come from PCB design work in Phase 6+. The doc's job here is to anchor the structure and ADR references so downstream work has a single board document to update.

## Goal Create the board spec skeleton at `docs/spec/pop-accel-8-board-v1.md`, listed as deliverable #2 in PLAN.md Section 10. The doc gathers board-level decisions (ADR-008 through ADR-014) so PCB, cooling, supply-chain, and funding work share a single board reference. Sections to include: - Overview (FluidPopV1 production board: 8 SoCs in 2x4 torus per ADR-010, designated master per ADR-008) - Form factor (OAM 2.0 per ADR-013) - Inter-chip fabric (PopLink 2D torus per ADR-009/010; non-coherent memory per ADR-011) - Memory subsystem (8 DDR5 RDIMMs, one per SoC per ADR-005) - Host interface (PCIe Gen4 x16 via master SoC only) - Power and thermal (per-chip 50 W typ / 70 W max per ADR-012; board-level budget ~400-560 W; cold-plate cooling per Section 15.11) - Stack-up and signal integrity (14-16 layer impedance-controlled, Megtron 6+ per Section 15.4) - BMC subsystem (WCH CH32V307 candidate per Section 15.8) - Connectors (Luxshare-ICT OAM-qualified per Section 15.9) - Assembly requirements (FC-BGA >1500 balls, X-ray / ball-shear / CSAM per Section 15.5) - Open questions (clock distribution, JTAG topology, telemetry side-band) ## Acceptance criteria - [ ] `docs/spec/pop-accel-8-board-v1.md` exists with the sections above - [ ] `Status: Draft skeleton` + `Owner: TBD` header - [ ] Each section has `TODO` markers and 2-3 line intent description - [ ] References ADR placeholders 008-014 explicitly - [ ] No fabricated dimensions or trace impedance numbers — only values already in PLAN.md - [ ] Cross-references PLAN.md Sections 10, 8.1 (board-level ADRs), 15.4/15.5/15.8/15.9/15.11 ## Plan refs Section 10 (deliverable #2), Section 8.1 (board-level ADRs), Section 11.2.B (production board cost frame), Sections 15.4/15.5/15.8/15.9/15.11 (supplier inputs) ## Notes Skeleton only — final mechanical/electrical numbers come from PCB design work in Phase 6+. The doc's job here is to anchor the structure and ADR references so downstream work has a single board document to update.