docs(spec): rewrite pop-accel-8-board-v1.md as Draft skeleton #88

Merged

navigator merged 1 commit from auto/issue-85-20260526T040052Z_issue85 into main

2026-05-26 01:05:45 -03:00

navigator commented

2026-05-26 01:03:42 -03:00

Owner

Summary

Replaces the one-paragraph Stub at docs/spec/pop-accel-8-board-v1.md with the board spec skeleton called for in PLAN.md Section 10 deliverable #2. Mirrors the structure of docs/spec/programming-model.md (Status / Owner / Tracks header, numbered TODO sections, no fabricated numbers, "Open questions" parking lot) so the chip, board, and software specs share a single shape.

Each section anchors to its board-level ADR (008-014) or PLAN.md supplier section (15.4 / 15.5 / 15.8 / 15.9 / 15.11). No mechanical, electrical, or thermal numbers introduced beyond what PLAN.md already holds — PCB design work in Phase 6+ (PLAN.md Section 11.2) produces the rest.

Acceptance criteria

docs/spec/pop-accel-8-board-v1.md exists with the eleven required sections
Status: Draft skeleton + Owner: TBD header
Each section has a TODO marker and a 2-3 line intent description
References ADR placeholders 008-014 explicitly
No fabricated dimensions or impedances — only PLAN.md values (50/70 W per chip, ~400-560 W aggregate, 14-16 layer Megtron 6+, ~1100/1500 ball FC-BGA, WCH CH32V307 BMC, Luxshare-ICT connectors)
Cross-references PLAN.md Sections 10, 8.1, 11.2, 15.4 / 15.5 / 15.8 / 15.9 / 15.11

Test plan

Markdown renders (line count 161, well under 600 LOC budget)
No off-limits paths touched (only docs/spec/)
No AI/Claude attribution in commit, body, or file

Closes #85

## Summary Replaces the one-paragraph Stub at `docs/spec/pop-accel-8-board-v1.md` with the board spec skeleton called for in PLAN.md Section 10 deliverable #2. Mirrors the structure of `docs/spec/programming-model.md` (Status / Owner / Tracks header, numbered TODO sections, no fabricated numbers, "Open questions" parking lot) so the chip, board, and software specs share a single shape. Each section anchors to its board-level ADR (008-014) or PLAN.md supplier section (15.4 / 15.5 / 15.8 / 15.9 / 15.11). No mechanical, electrical, or thermal numbers introduced beyond what PLAN.md already holds — PCB design work in Phase 6+ (PLAN.md Section 11.2) produces the rest. ## Acceptance criteria - [x] `docs/spec/pop-accel-8-board-v1.md` exists with the eleven required sections - [x] `Status: Draft skeleton` + `Owner: TBD` header - [x] Each section has a `TODO` marker and a 2-3 line intent description - [x] References ADR placeholders 008-014 explicitly - [x] No fabricated dimensions or impedances — only PLAN.md values (50/70 W per chip, ~400-560 W aggregate, 14-16 layer Megtron 6+, ~1100/1500 ball FC-BGA, WCH CH32V307 BMC, Luxshare-ICT connectors) - [x] Cross-references PLAN.md Sections 10, 8.1, 11.2, 15.4 / 15.5 / 15.8 / 15.9 / 15.11 ## Test plan - [x] Markdown renders (line count 161, well under 600 LOC budget) - [x] No off-limits paths touched (only `docs/spec/`) - [x] No AI/Claude attribution in commit, body, or file Closes #85

navigator added 1 commit

2026-05-26 01:03:42 -03:00

docs(spec): rewrite pop-accel-8-board-v1.md as Draft skeleton

build / scalafmt-check (pull_request) Successful in 4s

Details

build / sbt-compile (pull_request) Successful in 3s

Details

build / shell-lint (pull_request) Successful in 11s

Details

07c9666041

Replaces the one-paragraph Stub with the board spec skeleton called for in
PLAN.md Section 10 deliverable #2. Mirrors the structure used by
docs/spec/programming-model.md so the chip, board, and software specs
share a common shape (Status / Owner / Tracks header, numbered TODO
sections, no fabricated numbers, an "Open questions" parking lot).

Anchors every board-level decision to its ADR (008-014) or PLAN.md
section (15.4 / 15.5 / 15.8 / 15.9 / 15.11), so PCB, cooling,
supply-chain, and funding work share a single board reference instead
of redundantly citing the ADR set. No mechanical, electrical, or
thermal numbers introduced beyond what PLAN.md already holds.

Closes #85

navigator added the

ready-for-review

label

2026-05-26 01:03:49 -03:00

navigator commented

2026-05-26 01:04:29 -03:00

Author

Owner

VERDICT: PASS

PR #88 replaces the one-paragraph stub at docs/spec/pop-accel-8-board-v1.md with the 11-section board-level skeleton called for in PLAN.md §10 deliverable #2, mirroring the structure already established by programming-model.md and poplink-phy-if.md. The mechanical guardrails are all in place: existing CC-BY-SA-4.0 SPDX header preserved (diff starts at line 4 with content untouched above), single file touched matching Issue #85, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply. The doc is unusually careful about rule 7 — there's an explicit "No fabricated dimensions" callout at the top stating that anything not already in PLAN.md or an Accepted ADR stays as TODO, and the PR body itemises exactly which numbers come from where (50/70 W per chip from ADR-012, ~400/560 W aggregate from 8× arithmetic on those values, 14-16 layer Megtron 6+ from PLAN.md §15.4, ~1100/1500 ball FC-BGA from ADR-014 matching the figure already cited in PR #83, WCH CH32V307 BMC from §15.8, Luxshare-ICT connectors from §15.9). The aggregate math checks out (8×50=400, 8×70=560). Trace impedances, layer assignments, exact ball pitches, cold-plate flow rates, per-rail decoupling, JTAG topology, and clock distribution are all explicitly deferred. The Pro-variant power envelope (150/180 W) is flagged as a follow-up rather than baked into the Edu-targeted skeleton, and the "Open questions" §11 parks unresolved items with concrete deferral targets. Every numerical claim is attributed to a specific PLAN.md section or ADR (008–014), and the doc explicitly signals it should be updated alongside any ADR transitioning to Accepted or any §15 supplier pre-qualification closing.

Findings

None.

**VERDICT:** PASS PR #88 replaces the one-paragraph stub at `docs/spec/pop-accel-8-board-v1.md` with the 11-section board-level skeleton called for in PLAN.md §10 deliverable #2, mirroring the structure already established by `programming-model.md` and `poplink-phy-if.md`. The mechanical guardrails are all in place: existing `CC-BY-SA-4.0` SPDX header preserved (diff starts at line 4 with content untouched above), single file touched matching Issue #85, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply. The doc is unusually careful about rule 7 — there's an explicit "No fabricated dimensions" callout at the top stating that anything not already in PLAN.md or an Accepted ADR stays as TODO, and the PR body itemises exactly which numbers come from where (50/70 W per chip from ADR-012, ~400/560 W aggregate from 8× arithmetic on those values, 14-16 layer Megtron 6+ from PLAN.md §15.4, ~1100/1500 ball FC-BGA from ADR-014 matching the figure already cited in PR #83, WCH CH32V307 BMC from §15.8, Luxshare-ICT connectors from §15.9). The aggregate math checks out (8×50=400, 8×70=560). Trace impedances, layer assignments, exact ball pitches, cold-plate flow rates, per-rail decoupling, JTAG topology, and clock distribution are all explicitly deferred. The Pro-variant power envelope (150/180 W) is flagged as a follow-up rather than baked into the Edu-targeted skeleton, and the "Open questions" §11 parks unresolved items with concrete deferral targets. Every numerical claim is attributed to a specific PLAN.md section or ADR (008–014), and the doc explicitly signals it should be updated alongside any ADR transitioning to Accepted or any §15 supplier pre-qualification closing. ## Findings _None._

navigator added the

review:pass

label

2026-05-26 01:04:29 -03:00