rtl: scaffold rtl/ tree with chipyard.hash placeholder + module SPEC stubs #43

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navigator merged 1 commit from auto/issue-40-20260525T121803Z_issue40 into main 2026-05-25 11:31:07 -03:00
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Summary

Bootstraps the rtl/ directory tree referenced repeatedly in PLAN.md §6, §8.2, §12.3 and §13.3 so future Phase-1 RTL issues have a well-known place to land.

This PR is pure scaffolding — no Chisel sources, no Chipyard checkout, no build.sbt.

Files added

  • rtl/README.md — explains the layout and links each future module to its SPEC stub and the PLAN.md §12.3 verification floor
  • rtl/chipyard.hash — placeholder containing only # TODO: pin Chipyard 1.13.0 hash here (Phase 1 Week 4) (the real pin is owned by the toolchain-install issue)
  • rtl/src/pop/.gitkeep
  • rtl/src/pop/specs/<Module>.SPEC.md × 8 (one per module listed in PLAN.md §8.2 + §13.3):
    • PopRoCCRouter.SPEC.md
    • InterGemminiXbar.SPEC.md
    • InterChipFabric.SPEC.md
    • PCIeHostBridge.SPEC.md
    • MultiGemminiCluster.SPEC.md
    • FluidPopSoC.SPEC.md
    • PopSoCConfig.SPEC.md
    • PopLinkPHY_Behavioral.SPEC.md

Each SPEC stub: H1 title, Status: Stub, future source file path, plan/ADR refs, one-line purpose paraphrased from PLAN.md, and empty Interface / Behavior / Invariants / Coverage targets sections that explicitly reference the §12.3 thresholds (≥ 85 % line, ≥ 70 % condition) plus the §12.7 sign-off uplift.

Acceptance criteria (issue #40)

  • rtl/ directory exists with files listed above
  • rtl/chipyard.hash is a placeholder, NOT a real hash
  • Each SPEC.md stub names the file from §8.2 / §13.3 and references §12.3 per-module verification requirements
  • No Scala / Chisel source files created — only SPEC.md stubs and README
  • rtl/README.md cross-references PLAN.md §8.2 and notes the Chipyard clone happens via the toolchain-install issue

Constraints honoured

  • 251 LOC inserted (well under the 600 LOC budget)
  • No off-limits paths touched (no infra/forgejo/**, no Accepted ADRs, no LICENSE.md / CHANGELOG.md / PLAN.md)
  • Pre-commit hook passed without --no-verify

Test plan

  • git diff --cached --shortstat confirms 251-line scope
  • Pre-commit hook executed and accepted the staged set
  • Reviewer: spot-check that each SPEC stub references both PLAN.md §12.3 and the correct §8.2 / §13.3 source file path
  • Reviewer: confirm rtl/chipyard.hash contains only the TODO comment (no real hash)

Closes #40.

## Summary Bootstraps the `rtl/` directory tree referenced repeatedly in PLAN.md §6, §8.2, §12.3 and §13.3 so future Phase-1 RTL issues have a well-known place to land. This PR is **pure scaffolding** — no Chisel sources, no Chipyard checkout, no `build.sbt`. ## Files added - `rtl/README.md` — explains the layout and links each future module to its SPEC stub and the PLAN.md §12.3 verification floor - `rtl/chipyard.hash` — placeholder containing only `# TODO: pin Chipyard 1.13.0 hash here (Phase 1 Week 4)` (the real pin is owned by the toolchain-install issue) - `rtl/src/pop/.gitkeep` - `rtl/src/pop/specs/<Module>.SPEC.md` × 8 (one per module listed in PLAN.md §8.2 + §13.3): - `PopRoCCRouter.SPEC.md` - `InterGemminiXbar.SPEC.md` - `InterChipFabric.SPEC.md` - `PCIeHostBridge.SPEC.md` - `MultiGemminiCluster.SPEC.md` - `FluidPopSoC.SPEC.md` - `PopSoCConfig.SPEC.md` - `PopLinkPHY_Behavioral.SPEC.md` Each SPEC stub: H1 title, `Status: Stub`, future source file path, plan/ADR refs, one-line purpose paraphrased from PLAN.md, and empty `Interface` / `Behavior` / `Invariants` / `Coverage targets` sections that explicitly reference the §12.3 thresholds (≥ 85 % line, ≥ 70 % condition) plus the §12.7 sign-off uplift. ## Acceptance criteria (issue #40) - [x] `rtl/` directory exists with files listed above - [x] `rtl/chipyard.hash` is a placeholder, NOT a real hash - [x] Each SPEC.md stub names the file from §8.2 / §13.3 and references §12.3 per-module verification requirements - [x] No Scala / Chisel source files created — only SPEC.md stubs and README - [x] `rtl/README.md` cross-references PLAN.md §8.2 and notes the Chipyard clone happens via the toolchain-install issue ## Constraints honoured - 251 LOC inserted (well under the 600 LOC budget) - No off-limits paths touched (no `infra/forgejo/**`, no Accepted ADRs, no `LICENSE.md` / `CHANGELOG.md` / `PLAN.md`) - Pre-commit hook passed without `--no-verify` ## Test plan - [x] `git diff --cached --shortstat` confirms 251-line scope - [x] Pre-commit hook executed and accepted the staged set - [ ] Reviewer: spot-check that each SPEC stub references both PLAN.md §12.3 and the correct §8.2 / §13.3 source file path - [ ] Reviewer: confirm `rtl/chipyard.hash` contains only the TODO comment (no real hash) Closes #40.
rtl: scaffold rtl/ directory with chipyard.hash placeholder and module SPEC stubs
All checks were successful
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42c4c185b2
Bootstraps the rtl/ tree referenced by PLAN.md §6, §8.2, §12.3, and §13.3
so future Phase-1 RTL issues have well-known landing destinations.

Pure scaffolding — no Chisel sources, no Chipyard checkout. The actual
Chipyard 1.13.0 clone + hash pin remains tracked by the separate
toolchain-install issue and lands in Phase 1 Week 4.

Adds:
- rtl/README.md cross-referencing PLAN.md §8.2 / §12.3 / §13.3
- rtl/chipyard.hash placeholder ("# TODO: pin Chipyard 1.13.0 hash here ...")
- rtl/src/pop/.gitkeep
- rtl/src/pop/specs/<Module>.SPEC.md stubs for the eight modules listed
  in PLAN.md §8.2 + §13.3 (PopRoCCRouter, InterGemminiXbar,
  InterChipFabric, PCIeHostBridge, MultiGemminiCluster, FluidPopSoC,
  PopSoCConfig, PopLinkPHY_Behavioral). Each stub names the future
  .scala file and references the §12.3 per-module verification floor
  (≥ 85 % line / ≥ 70 % condition) plus the §12.7 sign-off thresholds.

Closes #40.
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fluidpop-bot approved these changes 2026-05-25 11:22:56 -03:00
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