rtl: PopLinkPHY_Behavioral skeleton + standalone sbt build #66

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navigator wants to merge 1 commit from auto/issue-51-20260525T202210Z_issue51 into main
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Closes #51

Summary

First Chisel module + minimal sbt project under rtl/:

  • rtl/src/pop/PopLinkPHY_Behavioral.scala --- skeleton Module + PopLinkPHYIO bundle, CHARRUA-1.2 header.
    • linkUp materialised (Bool); per-lane symbol streams, extended handshake, BER / status counters left as documented // TBD per SPEC §Interface blocks. No widths or lane counts invented (docs/spec/poplink-phy-if.md is itself a Stub; PLAN.md §13.3 does not yet pin them).
    • Output drain via io <> DontCare; SPEC §Behavior / §Invariants items pointed at follow-up issues.
  • rtl/tests/PopLinkPHY_Behavioral/PopLinkPHY_BehavioralSpec.scala --- chiseltest AnyFlatSpec with the single should "elaborate" case, AGPL-3.0-or-later header.
  • rtl/build.sbt + rtl/project/build.properties + rtl/.gitignore --- standalone sbt project, Chisel 6.5.0 / chiseltest 6.0.0 pinned to the same versions as Chipyard 1.13.0 (see rtl/chipyard.hash / ~/chipyard/build.sbt). Compile/scalaSource and Test/scalaSource are overridden to match the src/pop and tests/<Module> layout from rtl/README.md rather than sbt defaults.
  • rtl/README.md --- stale "no Scala sources, no build.sbt" line updated.

Validation (local, agent host)

  • sbt compile --- green (1 source compiled).
  • sbt Test/compile --- green.
  • sbt test --- 1 test, 1 passed (PopLinkPHY_BehavioralSpec elaborates the module).

No Chipyard checkout was required for these --- the standalone build resolves Chisel + chiseltest from Maven Central.

Out of scope (deferred to follow-up issues)

  • Behavioural model itself (line-rate, latency, injectable BER, drop / re-order knobs --- SPEC §Behavior).
  • Synthesis-translate-off guard (SPEC §Invariants).
  • Pinning PopLinkPHYIO widths / lane count / training FSM (Phase-1 PHY deliverable #2 --- PHY interface spec).
  • Coverage runs (SPEC §Coverage targets is a Phase-3 close obligation; this PR is skeleton + elaborate only).
  • Parent wiring: leaf module, no parent.

Off-limits

No ADR-017 off-limits paths touched. No commit hook bypass.

Closes #51 ## Summary First Chisel module + minimal sbt project under `rtl/`: - `rtl/src/pop/PopLinkPHY_Behavioral.scala` --- skeleton `Module` + `PopLinkPHYIO` bundle, CHARRUA-1.2 header. - `linkUp` materialised (Bool); per-lane symbol streams, extended handshake, BER / status counters left as documented `// TBD per SPEC §Interface` blocks. No widths or lane counts invented (docs/spec/poplink-phy-if.md is itself a Stub; PLAN.md §13.3 does not yet pin them). - Output drain via `io <> DontCare`; SPEC §Behavior / §Invariants items pointed at follow-up issues. - `rtl/tests/PopLinkPHY_Behavioral/PopLinkPHY_BehavioralSpec.scala` --- chiseltest `AnyFlatSpec` with the single `should "elaborate"` case, AGPL-3.0-or-later header. - `rtl/build.sbt` + `rtl/project/build.properties` + `rtl/.gitignore` --- standalone sbt project, Chisel 6.5.0 / chiseltest 6.0.0 pinned to the same versions as Chipyard 1.13.0 (see `rtl/chipyard.hash` / `~/chipyard/build.sbt`). `Compile/scalaSource` and `Test/scalaSource` are overridden to match the `src/pop` and `tests/<Module>` layout from `rtl/README.md` rather than sbt defaults. - `rtl/README.md` --- stale "no Scala sources, no build.sbt" line updated. ## Validation (local, agent host) - `sbt compile` --- green (1 source compiled). - `sbt Test/compile` --- green. - `sbt test` --- 1 test, 1 passed (`PopLinkPHY_BehavioralSpec` elaborates the module). No Chipyard checkout was required for these --- the standalone build resolves Chisel + chiseltest from Maven Central. ## Out of scope (deferred to follow-up issues) - Behavioural model itself (line-rate, latency, injectable BER, drop / re-order knobs --- SPEC §Behavior). - Synthesis-translate-off guard (SPEC §Invariants). - Pinning `PopLinkPHYIO` widths / lane count / training FSM (Phase-1 PHY deliverable #2 --- PHY interface spec). - Coverage runs (SPEC §Coverage targets is a Phase-3 close obligation; this PR is skeleton + elaborate only). - Parent wiring: leaf module, no parent. ## Off-limits No ADR-017 off-limits paths touched. No commit hook bypass.
rtl: PopLinkPHY_Behavioral skeleton + standalone sbt build
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74c0a9f43d
First Chisel module landing in rtl/. Skeleton-only per issue #51:
PopLinkPHYIO bundle (linkUp materialised; per-lane symbol streams,
extended handshake, BER counters intentionally left as TBD with
SPEC §Interface references --- docs/spec/poplink-phy-if.md is itself
a stub and widths / lane count / training-FSM are not pinned).
Behaviour (line-rate, latency, injectable BER, drop / re-order knobs)
lands in follow-up issues per SPEC §Behavior / §Invariants.

build.sbt is standalone, pinned to the same Chisel 6.5.0 + chiseltest
6.0.0 versions Chipyard 1.13.0 uses (rtl/chipyard.hash). Non-standard
source layout (src/pop, tests/<Module>) preserved from rtl/README.md
via Compile/Test scalaSource overrides.

Validation: sbt compile, sbt Test/compile, sbt test all green
locally (the AnyFlatSpec "should elaborate" case passes).

Licensing: CHARRUA-1.2 on the Scala source per LICENSE.md mapping;
AGPL-3.0-or-later on the test.
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Closing as stale. Original branch was based off main from before #59/#60/#67 landed and the diff now collides with files those PRs added. Issue #51 can be re-queued; resolver will start from current main.

Closing as stale. Original branch was based off main from before #59/#60/#67 landed and the diff now collides with files those PRs added. Issue #51 can be re-queued; resolver will start from current main.
navigator closed this pull request 2026-05-25 19:48:59 -03:00
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