spec(PopLinkPHY_Behavioral): promote PopLinkPHY_Behavioral.SPEC.md to Draft #95

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navigator merged 1 commit from spec/poplinkphy_behavioral-draft into main 2026-05-26 02:26:53 -03:00

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navigator commented 2026-05-26 02:25:40 -03:00

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Refs #51 (companion Chisel skeleton, area:rtl).
Refs #80 (spec-designer role onboarding).

This PR is opened by the autonomous spec-designer role; per
infra/ops/agents/roles/spec-designer.sh the role is designer-driven
and runs without a dedicated source issue, so no Closes # is attached.
If the swarm policy requires a tracking issue per promotion, the
follow-up tweak belongs in the role script, not in this SPEC change.

Summary

Promotes rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md from
Status: Stub to Status: Draft. No behaviour, no Chisel, no
edits outside the single SPEC file. The IO contract is pinned to
PLAN.md sections and to the sibling SPEC already in Draft
(InterChipFabric); widths and per-signal shapes that no source
pins are recorded as _Open question:_ rather than invented.

Resolved TBDs

• §Interface — PopLinkPHYIO bundle (shape-identical to the
  production PHY): pinned to PLAN.md §13.3 ("PopLinkPHYIO
  Chisel bundle decouples PHY from upper layers. Behavioral PHY for
  Phase 1 simulation (PopLinkPHY_Behavioral.scala)") and to the
  consumer surface in the Draft sibling
  rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface ("Each
  port presents the PopLinkPHYIO Chisel bundle per PLAN.md
  §13.3"). The signal-class enumeration is the one already in
  docs/spec/poplink-phy-if.md §2.
• §Interface — sim-only configuration parameters (line rate,
  latency, BER, drop / re-order knobs): framed as Chisel
  construction parameters (not in-band PopLinkPHYIO signals),
  pinned to PLAN.md §13.4 deliverable #1 framing ("Behavioral RTL
  model") and to the PLAN.md §12.4 verification path the knobs
  exist to drive ("single-link bring-up (>= 10^9 cycles); multi-VC
  stress; 2-chip and 8-chip torus; deadlock-freedom formal; BER
  injection (tolerate 10^-6 raw BER)").
• §Interface — clock-domain presentation (degenerate same-clock
  model): consistent with PLAN.md §13.4 "Behavioral RTL model"
  framing and with the Draft sibling
  rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface consuming
  the bundle without analog-domain assumptions.
• §Behavior — bit-exact symbol passthrough at zero BER: lifted
  from the Stub's existing bit-exact invariant into a behavior
  statement; the precondition the sibling Draft InterChipFabric
  ARQ tests rely on.
• §Behavior — configurable BER injection for §12.4 ARQ stress:
  pinned to PLAN.md §12.4 ("BER injection (tolerate 10^-6 raw
  BER)") and to the Draft sibling
  rtl/src/pop/specs/InterChipFabric.SPEC.md §Behavior ARQ surface
  (PLAN.md §3.4: "selective-repeat, 64-pkt window per VC, 1 µs
  retransmit timeout"). Reading channel is the ber_count hook in
  docs/spec/poplink-phy-if.md §6.
• §Behavior — degenerate training / link-up FSM: pinned to
  PLAN.md §3.4 ("Link state machine: RESET / INIT / TRAINING /
  ACTIVE / ERROR") in degenerate form (instant or configured-latency
  transitions); matches docs/spec/poplink-phy-if.md §5.
• §Behavior — sim-only drop / re-order knobs: framed as
  sim-only knobs that stress the deadlock argument of PLAN.md §3.5
  ("Routing: dimension-order (XY). Deadlock-free with 2 VCs.") and
  the Draft sibling
  rtl/src/pop/specs/InterChipFabric.SPEC.md §Invariants
  ("Deadlock-free under any legal traffic pattern"). Knobs do not
  advertise behaviour the production PHY would not exhibit at the
  link level.
• §Invariants — bit-exact symbol passthrough at BER = 0:
  preserved verbatim from the Stub.
• §Invariants — injected BER reaches InterChipFabric so 10⁻⁶
  raw-BER tolerance can be measured (§12.4): preserved verbatim
  from the Stub.
• §Invariants — never synthesised, sim-only guard required:
  preserved verbatim from the Stub.
• §Invariants — same public PopLinkPHYIO bundle as the
  production PHY: pinned to PLAN.md §13.3 / §13.2 (PHY-1 open
  academic / PHY-2 commercial IP / PHY-3 academic partnership must
  all conform to the same bundle). Cross-checked against the Draft
  sibling
  rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface which
  consumes the bundle on its PHY-facing quad-port.
• §Invariants — Phase-1 stand-in only, not the sign-off PHY:
  pinned to PLAN.md §13.4 / §13.5 / §12.7 (sign-off thresholds
  apply to the production PHY, not to this behavioral file —
  already noted in the Stub's §Coverage targets, restated as an
  invariant).

Open questions (recorded as _Open question:_ in the SPEC)

• Concrete per-signal widths and per-link lane count on the
  PopLinkPHYIO bundle — pending the PHY-option selection track
  of PLAN.md §13.2 (the same triple docs/spec/poplink-phy-if.md §3 defers).
• Default sim-only knob values (line rate, latency) and per-knob
  unit (cycles vs absolute time) — pending the same PHY-option
  selection.
• Whether the behavioral PHY also models a configurable per-lane
  skew between TX and RX symbol streams.
• Exact per-state configurable latencies of the training FSM, and
  whether the ERROR state is entered automatically when injected
  BER crosses a threshold (tracks the matching Open question on
  the Draft sibling InterChipFabric §Behavior).
• Drop / re-order knob semantics (drop-probability distribution,
  re-order window depth, per-lane vs aggregated application).

Constraint check

• **Status:** line flipped Stub → Draft.
• Every TBD resolved (pin to PLAN / sibling Draft, or recorded
  as _Open question:_). No fabricated widths or signal sets.
• Only rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md
  changes (ADR-017 off-limits path policy honoured).
• All ADR / PLAN refs from the Stub preserved (PLAN.md §13.3,
  §13.4, §12.3, §12.7, §13.2, §13.5, ADR-009,
  docs/spec/poplink-phy-if.md). Draft body cites additional
  refs the body relies on (PLAN.md §3.3, §3.4, §3.5, §12.4,
  sibling Draft InterChipFabric.SPEC.md) — added refs only,
  none removed.
• Sibling Drafts cited as pin sources only when actually in
  Draft (InterChipFabric). Stub siblings (PopRoCCRouter,
  PopSoCConfig, PopLinkPHY_Behavioral itself) are not used
  as Draft-pin sources.
• ## Promotion history appended with the 2026-05-26 entry.
• No fabricated technical claims: every number quoted
  (4 Gb/s/lane, 4 lanes/port, 16-32 Gb/s/lane, 8 lanes/port,
  64-pkt ARQ window, 1 µs retransmit, 10⁻⁶ raw BER, 95/85 %
  coverage gates) has a PLAN.md section as its source and is
  quoted verbatim.

Refs #51 (companion Chisel skeleton, area:rtl). Refs #80 (spec-designer role onboarding). This PR is opened by the autonomous `spec-designer` role; per `infra/ops/agents/roles/spec-designer.sh` the role is designer-driven and runs without a dedicated source issue, so no `Closes #` is attached. If the swarm policy requires a tracking issue per promotion, the follow-up tweak belongs in the role script, not in this SPEC change. ## Summary Promotes `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` from **Status: Stub** to **Status: Draft**. No behaviour, no Chisel, no edits outside the single SPEC file. The IO contract is pinned to PLAN.md sections and to the sibling SPEC already in Draft (`InterChipFabric`); widths and per-signal shapes that no source pins are recorded as `_Open question:_` rather than invented. ## Resolved TBDs - **§Interface — `PopLinkPHYIO` bundle (shape-identical to the production PHY)**: pinned to PLAN.md §13.3 ("`PopLinkPHYIO` Chisel bundle decouples PHY from upper layers. Behavioral PHY for Phase 1 simulation (`PopLinkPHY_Behavioral.scala`)") and to the consumer surface in the Draft sibling `rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface` ("Each port presents the `PopLinkPHYIO` Chisel bundle per PLAN.md §13.3"). The signal-class enumeration is the one already in `docs/spec/poplink-phy-if.md §2`. - **§Interface — sim-only configuration parameters (line rate, latency, BER, drop / re-order knobs)**: framed as Chisel construction parameters (not in-band `PopLinkPHYIO` signals), pinned to PLAN.md §13.4 deliverable #1 framing ("Behavioral RTL model") and to the PLAN.md §12.4 verification path the knobs exist to drive ("single-link bring-up (>= 10^9 cycles); multi-VC stress; 2-chip and 8-chip torus; deadlock-freedom formal; BER injection (tolerate 10^-6 raw BER)"). - **§Interface — clock-domain presentation (degenerate same-clock model)**: consistent with PLAN.md §13.4 "Behavioral RTL model" framing and with the Draft sibling `rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface` consuming the bundle without analog-domain assumptions. - **§Behavior — bit-exact symbol passthrough at zero BER**: lifted from the Stub's existing bit-exact invariant into a behavior statement; the precondition the sibling Draft InterChipFabric ARQ tests rely on. - **§Behavior — configurable BER injection for §12.4 ARQ stress**: pinned to PLAN.md §12.4 ("BER injection (tolerate 10^-6 raw BER)") and to the Draft sibling `rtl/src/pop/specs/InterChipFabric.SPEC.md §Behavior` ARQ surface (PLAN.md §3.4: "selective-repeat, 64-pkt window per VC, 1 µs retransmit timeout"). Reading channel is the `ber_count` hook in `docs/spec/poplink-phy-if.md §6`. - **§Behavior — degenerate training / link-up FSM**: pinned to PLAN.md §3.4 ("Link state machine: RESET / INIT / TRAINING / ACTIVE / ERROR") in degenerate form (instant or configured-latency transitions); matches `docs/spec/poplink-phy-if.md §5`. - **§Behavior — sim-only drop / re-order knobs**: framed as sim-only knobs that stress the deadlock argument of PLAN.md §3.5 ("Routing: dimension-order (XY). Deadlock-free with 2 VCs.") and the Draft sibling `rtl/src/pop/specs/InterChipFabric.SPEC.md §Invariants` ("Deadlock-free under any legal traffic pattern"). Knobs do not advertise behaviour the production PHY would not exhibit at the link level. - **§Invariants — bit-exact symbol passthrough at BER = 0**: preserved verbatim from the Stub. - **§Invariants — injected BER reaches `InterChipFabric` so 10⁻⁶ raw-BER tolerance can be measured (§12.4)**: preserved verbatim from the Stub. - **§Invariants — never synthesised, sim-only guard required**: preserved verbatim from the Stub. - **§Invariants — same public `PopLinkPHYIO` bundle as the production PHY**: pinned to PLAN.md §13.3 / §13.2 (PHY-1 open academic / PHY-2 commercial IP / PHY-3 academic partnership must all conform to the same bundle). Cross-checked against the Draft sibling `rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface` which consumes the bundle on its PHY-facing quad-port. - **§Invariants — Phase-1 stand-in only, not the sign-off PHY**: pinned to PLAN.md §13.4 / §13.5 / §12.7 (sign-off thresholds apply to the production PHY, not to this behavioral file — already noted in the Stub's §Coverage targets, restated as an invariant). ## Open questions (recorded as `_Open question:_` in the SPEC) - Concrete per-signal widths and per-link lane count on the `PopLinkPHYIO` bundle — pending the PHY-option selection track of PLAN.md §13.2 (the same triple `docs/spec/poplink-phy-if.md §3` defers). - Default sim-only knob values (line rate, latency) and per-knob unit (cycles vs absolute time) — pending the same PHY-option selection. - Whether the behavioral PHY also models a configurable per-lane skew between TX and RX symbol streams. - Exact per-state configurable latencies of the training FSM, and whether the ERROR state is entered automatically when injected BER crosses a threshold (tracks the matching Open question on the Draft sibling InterChipFabric §Behavior). - Drop / re-order knob semantics (drop-probability distribution, re-order window depth, per-lane vs aggregated application). ## Constraint check - [x] `**Status:**` line flipped Stub → Draft. - [x] Every TBD resolved (pin to PLAN / sibling Draft, or recorded as `_Open question:_`). No fabricated widths or signal sets. - [x] Only `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` changes (ADR-017 off-limits path policy honoured). - [x] All ADR / PLAN refs from the Stub preserved (PLAN.md §13.3, §13.4, §12.3, §12.7, §13.2, §13.5, ADR-009, `docs/spec/poplink-phy-if.md`). Draft body cites additional refs the body relies on (PLAN.md §3.3, §3.4, §3.5, §12.4, sibling Draft `InterChipFabric.SPEC.md`) — added refs only, none removed. - [x] Sibling Drafts cited as pin sources only when actually in Draft (`InterChipFabric`). Stub siblings (`PopRoCCRouter`, `PopSoCConfig`, `PopLinkPHY_Behavioral` itself) are not used as Draft-pin sources. - [x] `## Promotion history` appended with the 2026-05-26 entry. - [x] No fabricated technical claims: every number quoted (4 Gb/s/lane, 4 lanes/port, 16-32 Gb/s/lane, 8 lanes/port, 64-pkt ARQ window, 1 µs retransmit, 10⁻⁶ raw BER, 95/85 % coverage gates) has a PLAN.md section as its source and is quoted verbatim.

navigator added 1 commit 2026-05-26 02:25:40 -03:00

spec(PopLinkPHY_Behavioral): promote PopLinkPHY_Behavioral.SPEC.md to Draft ... 664a5c2e7b

Flips `Status: Stub` → `Status: Draft` on
`rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` and fills the four
TBD section bodies. No behaviour, no Chisel, no edits outside the
single SPEC file (ADR-017 off-limits policy honoured). The IO
contract is pinned to PLAN.md sections and to a sibling SPEC already
in Draft (`InterChipFabric`); widths and per-signal shapes that no
source pins are recorded as `_Open question:_` rather than invented.

Resolved TBDs (pinned):
- §Interface — `PopLinkPHYIO` bundle: pinned to PLAN.md §13.3
  ("`PopLinkPHYIO` Chisel bundle decouples PHY from upper layers")
  and to the consumer surface in the Draft sibling
  `rtl/src/pop/specs/InterChipFabric.SPEC.md §Interface`. The
  signal-class enumeration is the one already in
  `docs/spec/poplink-phy-if.md §2`.
- §Interface — sim-only configuration parameters: framed as Chisel
  construction parameters (not in-band signals), pinned to PLAN.md
  §13.4 deliverable #1 framing ("Behavioral RTL model") and the
  PLAN.md §12.4 verification path it exists to drive.
- §Interface — clock-domain presentation: degenerate same-clock
  model, consistent with PLAN.md §13.4's "Behavioral RTL model"
  framing and the Draft sibling InterChipFabric consuming the
  bundle without analog-domain assumptions.
- §Behavior — bit-exact passthrough at BER=0: lifted from the
  Stub's invariant into a behavior statement.
- §Behavior — BER injection for §12.4 stress: pinned to PLAN.md
  §12.4 ("BER injection (tolerate 10^-6 raw BER)") and to the
  Draft sibling InterChipFabric ARQ (PLAN.md §3.4: "selective-
  repeat, 64-pkt window per VC, 1 µs retransmit timeout").
- §Behavior — degenerate training/link-up FSM: pinned to PLAN.md
  §3.4 ("Link state machine: RESET / INIT / TRAINING / ACTIVE /
  ERROR") in degenerate form.
- §Behavior — drop / re-order knobs: framed as sim-only knobs that
  stress the deadlock argument of PLAN.md §3.5 and the Draft
  sibling InterChipFabric's "Deadlock-free under any legal traffic
  pattern" invariant.
- §Invariants — bit-exact passthrough / injected BER reaches fabric /
  never synthesised: preserved verbatim from the Stub.
- §Invariants — shape-identical `PopLinkPHYIO` bundle to the
  production PHY: pinned to PLAN.md §13.3 / §13.2 (PHY-1 / PHY-2 /
  PHY-3 must all conform to the same bundle).
- §Invariants — Phase-1 stand-in only: pinned to PLAN.md §13.4 /
  §13.5 / §12.7 (sign-off thresholds apply to the production PHY,
  not to this behavioral file — already noted in the Stub's
  §Coverage targets, restated as an invariant).

Open questions (recorded as `_Open question:_` in the SPEC):
- Concrete per-signal widths and per-link lane count on the
  `PopLinkPHYIO` bundle — pending the PHY-option selection track
  of PLAN.md §13.2 (the same triple `docs/spec/poplink-phy-if.md
  §3` defers).
- Default sim-only knob values (line rate, latency) and per-knob
  unit (cycles vs absolute time) — pending the PHY-option
  selection.
- Whether the behavioral PHY also models per-lane TX/RX skew.
- Exact per-state configurable latencies of the training FSM and
  whether the ERROR state is entered automatically when injected
  BER crosses a threshold.
- Drop / re-order knob semantics (probability distribution,
  re-order window depth, per-lane vs aggregated application).

Constraint check:
- `**Status:**` line flipped Stub → Draft.
- Every TBD resolved (pin to PLAN / sibling Draft, or recorded as
  `_Open question:_`). No fabricated widths or signal sets.
- Only `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` changes.
- All Stub cross-refs preserved (PLAN.md §13.3, §13.4, §12.3,
  §12.7, §13.2, §13.5, ADR-009, `docs/spec/poplink-phy-if.md`).
  Draft body cites additional refs it relies on (PLAN.md §3.3,
  §3.4, §3.5, §12.4, sibling Draft InterChipFabric) — added only,
  none removed.
- `## Promotion history` appended with the 2026-05-26 entry.
- No fabricated technical claims: every number quoted (4 Gb/s/lane,
  4 lanes/port, 16-32 Gb/s/lane, 8 lanes/port, 64-pkt ARQ window,
  1 µs retransmit, 10⁻⁶ raw BER, 95/85 % coverage gates) has a
  PLAN.md section as its source and is quoted verbatim.

Refs #51 (companion Chisel skeleton, area:rtl).
Refs #80 (spec-designer role onboarding).

navigator added the

ready-for-review

label 2026-05-26 02:25:44 -03:00

navigator commented 2026-05-26 02:26:28 -03:00

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VERDICT: PASS

PR #95 promotes rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md from Stub to Draft following the same disciplined pattern as PR #87, PR #91, PR #92, PR #93, and PR #94. Mechanical guardrails pass: existing SPDX header preserved (diff starts at line 4), single file touched, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply, autonomous spec-designer role explains missing Closes #. Rule 7 is meticulously handled: every concrete claim is presented as a verbatim quote from a PLAN.md section, with the source pinned inline. Cross-checking against approved PRs in this thread: PLAN.md §3.3 per-port bandwidth envelope quotes ("Edu: source-synchronous LVDS, 4 Gb/s/lane, 4 lanes/port = 16 Gb/s/port/dir" and "Pro: commercial SerDes 16-32 Gb/s/lane (NRZ/PAM4), 8 lanes/port = 128-256 Gb/s/port/dir") match PR #91 verbatim; PLAN.md §3.4 quotes ("selective-repeat, 64-pkt window per VC, 1 µs retransmit timeout"; "Link state machine: RESET / INIT / TRAINING / ACTIVE / ERROR") match PR #91; PLAN.md §3.5 deadlock-freedom quote ("Routing: dimension-order (XY). Deadlock-free with 2 VCs.") matches PR #91 and PR #92; PLAN.md §12.4 BER tolerance target ("BER injection (tolerate 10^-6 raw BER)") and §12.7 sign-off line ("ARQ tolerates 10^-6 raw BER") match PR #91; PLAN.md §13.3 PopLinkPHYIO decoupling quote matches PR #91. New PLAN.md §13.5 framing quote ("PHY is a real risk. Partnership strategy primary; IP licensing fallback. Custom-from-scratch analog NOT in scope.") is honestly cited as the source of the "Phase-1 stand-in only" invariant. Critically, every facet that could tempt fabrication (concrete per-signal widths, lane count, default knob values for line-rate and latency, per-knob units cycles vs absolute time, per-lane TX/RX skew model, per-state FSM latencies, automatic ERROR entry on BER threshold, drop/re-order knob semantics) is honestly parked as Open Question tied to pending PHY-option selection (PLAN.md §13.2 / §13.5) rather than invented. The invariant that the sign-off thresholds of PLAN.md §12.7 (95/85% coverage, formal proofs, 30 consecutive greens, zero sev-1/2 bugs) apply to the production PHY and not to this behavioral file is the right framing — explicit at the §Coverage targets level and now restated as the "Phase-1 stand-in only" invariant. Sibling Draft references (InterChipFabric §Interface/§Behavior/§Invariants) cite a SPEC that is in fact Draft per PR #91; Stub-status siblings are not used as Draft-pin sources. The PR body's explicit list of numeric values quoted from PLAN.md verbatim (4 Gb/s/lane, 4 lanes/port, 16-32 Gb/s/lane, 8 lanes/port, 64-pkt ARQ window, 1 µs retransmit, 10⁻⁶ raw BER, 95/85% coverage gates) is exactly the discipline rule 7 asks for. Promotion history entry is appropriate.

Findings

None.

<!-- agent:review verdict=PASS ts=1779773188 --> **VERDICT:** PASS PR #95 promotes `rtl/src/pop/specs/PopLinkPHY_Behavioral.SPEC.md` from Stub to Draft following the same disciplined pattern as PR #87, PR #91, PR #92, PR #93, and PR #94. Mechanical guardrails pass: existing SPDX header preserved (diff starts at line 4), single file touched, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply, autonomous `spec-designer` role explains missing `Closes #`. Rule 7 is meticulously handled: every concrete claim is presented as a verbatim quote from a PLAN.md section, with the source pinned inline. Cross-checking against approved PRs in this thread: PLAN.md §3.3 per-port bandwidth envelope quotes ("Edu: source-synchronous LVDS, 4 Gb/s/lane, 4 lanes/port = 16 Gb/s/port/dir" and "Pro: commercial SerDes 16-32 Gb/s/lane (NRZ/PAM4), 8 lanes/port = 128-256 Gb/s/port/dir") match PR #91 verbatim; PLAN.md §3.4 quotes ("selective-repeat, 64-pkt window per VC, 1 µs retransmit timeout"; "Link state machine: RESET / INIT / TRAINING / ACTIVE / ERROR") match PR #91; PLAN.md §3.5 deadlock-freedom quote ("Routing: dimension-order (XY). Deadlock-free with 2 VCs.") matches PR #91 and PR #92; PLAN.md §12.4 BER tolerance target ("BER injection (tolerate 10^-6 raw BER)") and §12.7 sign-off line ("ARQ tolerates 10^-6 raw BER") match PR #91; PLAN.md §13.3 PopLinkPHYIO decoupling quote matches PR #91. New PLAN.md §13.5 framing quote ("PHY is a real risk. Partnership strategy primary; IP licensing fallback. Custom-from-scratch analog NOT in scope.") is honestly cited as the source of the "Phase-1 stand-in only" invariant. Critically, every facet that could tempt fabrication (concrete per-signal widths, lane count, default knob values for line-rate and latency, per-knob units cycles vs absolute time, per-lane TX/RX skew model, per-state FSM latencies, automatic ERROR entry on BER threshold, drop/re-order knob semantics) is honestly parked as Open Question tied to pending PHY-option selection (PLAN.md §13.2 / §13.5) rather than invented. The invariant that the sign-off thresholds of PLAN.md §12.7 (95/85% coverage, formal proofs, 30 consecutive greens, zero sev-1/2 bugs) apply to the production PHY and *not* to this behavioral file is the right framing — explicit at the §Coverage targets level and now restated as the "Phase-1 stand-in only" invariant. Sibling Draft references (InterChipFabric §Interface/§Behavior/§Invariants) cite a SPEC that is in fact Draft per PR #91; Stub-status siblings are not used as Draft-pin sources. The PR body's explicit list of numeric values quoted from PLAN.md verbatim (4 Gb/s/lane, 4 lanes/port, 16-32 Gb/s/lane, 8 lanes/port, 64-pkt ARQ window, 1 µs retransmit, 10⁻⁶ raw BER, 95/85% coverage gates) is exactly the discipline rule 7 asks for. Promotion history entry is appropriate. ## Findings _None._

navigator added the

review:pass

label 2026-05-26 02:26:28 -03:00

fluidpop-bot approved these changes 2026-05-26 02:26:53 -03:00

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CI green (head 664a5c2e7b), auto-approving

CI green (head 664a5c2e7bcb5dccc11433135ca959776a1ac39f), auto-approving

navigator merged commit 5947b10928 into main 2026-05-26 02:26:53 -03:00

navigator referenced this pull request from a commit 2026-05-26 02:26:54 -03:00

spec(PopLinkPHY_Behavioral): promote PopLinkPHY_Behavioral.SPEC.md to Draft (#95)

navigator referenced this pull request 2026-05-26 02:43:17 -03:00

spec(PopRoCCRouter): promote PopRoCCRouter.SPEC.md to Draft #96

navigator referenced this pull request 2026-05-26 02:59:54 -03:00

spec(PopSoCConfig): promote PopSoCConfig.SPEC.md to Draft #97

navigator referenced this pull request 2026-05-26 13:43:23 -03:00

rtl: PopLinkPHY_Behavioral skeleton + chiseltest elaborate #106

navigator referenced this pull request 2026-05-26 18:12:06 -03:00

rtl: PopLinkPHY_Behavioral v1 — configurable line-rate + BER injection + drop knobs #113

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swarm:quarantined

Escalation tripwire fired; resolver tried off-limits paths

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phase:1

ready-for-review

review:findings

review:pass

risk:tripwire

swarm:quarantined

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Fluid/fluidpop-v1!95

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