spec(InterGemminiXbar): promote InterGemminiXbar.SPEC.md to Draft #92
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Delete branch "spec/intergemminixbar-draft"
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Refs #49 (companion Chisel skeleton, area:rtl, closed via #68).
Refs #80 (spec-designer role onboarding).
This PR is opened by the autonomous
spec-designerrole; perinfra/ops/agents/roles/spec-designer.shthe role is designer-drivenand runs without a dedicated source issue, so no
Closes #is attached.Summary
Promotes
rtl/src/pop/specs/InterGemminiXbar.SPEC.mdfromStatus: Stub to Status: Draft. No behaviour, no Chisel, no
edits outside the single SPEC file. The IO contract is pinned to ADRs
that already commit values; widths and per-port shapes no source pins
are recorded as
_Open question:_rather than invented.Resolved TBDs
N×N: pinned to ADR-003 Decision(4×4 Edu, 16×16 Pro) combined with ADR-001 Decision
(4 Gemminis Edu / 16 Pro); variant selector is
PopSoCConfigper PLAN.md §8.2 (
FluidPopMasterConfig/FluidPopSlaveConfig).("connecting scratchpad ports directly").
ADR-004 Decision (Edu 256 KiB SP + 64 KiB acc per Gemmini;
Pro 1 MiB SP + 256 KiB acc).
considered (shared-bus rejected on contention grounds).
ADR-003 Consequences ("Full any-to-any with low latency").
ADR-003 Alternatives considered (ring/torus, shared bus
rejected) — may not be substituted.
("Local Gemminis must exchange tile data without going through L2
(would bottleneck on bandwidth)").
("Cross-chip data movement is explicit via PopLink transactions")
InterChipFabric.SPEC.md §Behavior.("Within a chip, 4 Gemminis share L2 coherently").
N ∈ {4,…,16}:ADR-003 Consequences ("Crossbar grows quadratically with N;
manageable at 4-16"); variant switch PLAN.md §8.2.
§12.7) and unit-bench / golden-model requirement.
Open questions (no source pins)
response ordering versus request order) — upstream Gemmini
scratchpad port format lands once the Chipyard pin in PLAN.md §6
Week 4 (
rtl/chipyard.hash) reveals it.versus base-limit), and programming discipline (memory-mapped CSR
versus RoCC-config versus tie-off) — tracks
MultiGemminiCluster.SPEC.md §Interface(Status: Stub)./ occupancy side-band) and per-flit versus per-transaction
granularity — not pinned by ADR-003.
"round-robin baseline" was an informal placeholder, not pinned by
ADR-003 Decision or Consequences).
versus always-registered (vs PLAN.md §2.2 Edu frequency target
"800 MHz – 1 GHz").
floorplan synthesis and §12.7 sign-off coverage.
Constraints honoured
rtl/src/pop/specs/InterGemminiXbar.SPEC.mdchanges(ADR-017 off-limits paths).
§12.3, ADR-003); ADR-001, ADR-004, ADR-011, and PLAN §2.2 / §6 /
§9 / §12.7 are added as additional pins. Sibling Draft SPEC
InterChipFabric.SPEC.mdand sibling StubMultiGemminiCluster.SPEC.mdreferenced; no other sibling SPECis currently in Draft for InterGemminiXbar to depend on.
schedule promises; numeric values are quoted from PLAN.md or
ADRs verbatim.
Promotes rtl/src/pop/specs/InterGemminiXbar.SPEC.md from Status: Stub to Status: Draft. No behaviour, no Chisel, no edits outside the single SPEC file. The IO contract is pinned to ADRs that already commit values; widths and per-port shapes no source pins are recorded as _Open question:_ rather than invented. Resolved TBDs: - §Interface — port count N×N: ADR-003 Decision (4×4 Edu, 16×16 Pro) combined with ADR-001 Decision (4 Gemminis Edu / 16 Pro); variant switch is PopSoCConfig per PLAN.md §8.2. - §Interface — direct scratchpad attach: ADR-003 Decision ("connecting scratchpad ports directly"). - §Interface — programmable routing-table motivation: ADR-004 Decision (Edu 256 KiB SP + 64 KiB acc / Pro 1 MiB SP + 256 KiB acc per Gemmini). - §Interface — back-pressure mandatory: ADR-003 Alternatives considered (shared-bus rejected on contention). - §Behavior — non-blocking N×N crossbar: ADR-003 Decision + ADR-003 Consequences ("Full any-to-any with low latency"). - §Behavior — alternatives ruled out: ADR-003 Alternatives considered (ring/torus, shared bus rejected). - §Behavior — cross-tile traffic bypasses L2: ADR-003 Context. - §Behavior — cross-chip out of scope: ADR-011 Decision + sibling Draft SPEC InterChipFabric.SPEC.md §Behavior. - §Behavior — intra-chip coherence: ADR-011 Decision ("Within a chip, 4 Gemminis share L2 coherently"). - §Invariants — crossbar-size bound: ADR-003 Consequences ("manageable at 4-16"); variant switch PLAN.md §8.2. - §Coverage targets — preserved verbatim (PLAN.md §12.3 / §12.7). Open questions (no source pins): - Scratchpad-side bundle shape (data width, request-ID width, response ordering) — pending Chipyard pin per PLAN.md §6 Week 4. - Routing-table entry count, address-range encoding, programming discipline — tracks MultiGemminiCluster.SPEC.md §Interface (Stub). - Back-pressure encoding (ready/valid vs credit-based). - Arbitration policy at egress contention (Stub's "round-robin baseline" was an informal placeholder, not pinned by ADR-003). - Zero-cycle bypass permitted vs always-registered (vs PLAN.md §2.2 800 MHz – 1 GHz Edu frequency target). - Concrete worst-case latency bound — defers to PLAN.md §9 Phase 4 floorplan synthesis and §12.7 sign-off coverage. Constraints honoured: - Only rtl/src/pop/specs/InterGemminiXbar.SPEC.md changes (ADR-017). - All ADR / PLAN refs from the Stub are preserved (PLAN §8.2, §12.3, ADR-003); ADR-001, ADR-004, ADR-011, PLAN §2.2 / §6 / §9 / §12.7 added as additional pins. Sibling Draft SPEC InterChipFabric and sibling Stub MultiGemminiCluster referenced. - No fabricated widths, latencies, vendor commitments, or schedule promises.VERDICT: PASS
PR #92 promotes
rtl/src/pop/specs/InterGemminiXbar.SPEC.mdfrom Stub to Draft following the same disciplined pattern as PR #87 (FluidPopSoC) and PR #91 (InterChipFabric). Mechanical guardrails pass: existing SPDX header preserved, single file touched, no AI/Anthropic attribution, no off-limits paths, no Chisel module so rules 4–6 don't apply. MissingCloses #is explained transparently — autonomousspec-designerrole with no per-promotion tracking issue. Rule 7 is meticulously handled: every concrete claim is a verbatim quote from an ADR Decision, Consequences, Alternatives, or Context section. The two key claims that I had previously flagged as possibly fabricated on earlier reviews now have explicit source pins, retroactively vindicating those PRs: (a) PR #81's"Per ADR-003 the topology is 4×4 today (16×16 in Pro)"comment was correct — ADR-003 Decision is quoted verbatim here as"Implement a 4x4 crossbar (InterGemminiXbar.scala) connecting scratchpad ports directly. Pro config scales to 16x16 crossbar", which combined with ADR-001's"4 Gemminis per SoC in the Edu configuration, parameterized to 16 in the Pro configuration"confirms the scaling; (b) PR #89's"256 KiB scratchpad + 64 KiB accumulator per Gemmini tile (ADR-004)"claim that I flagged as potentially containing fabricated accumulator size is also confirmed here as a verbatim ADR-004 Decision quote — Edu"256 KiB SP + 64 KiB accumulator per Gemmini"and Pro"1 MiB SP + 256 KiB accumulator". The remaining quotes — ADR-003 Context ("Local Gemminis must exchange tile data without going through L2 (would bottleneck on bandwidth)"), ADR-003 Alternatives ("Ring/torus (rejected: latency for opposite endpoints). Shared bus (rejected: contention)"), ADR-003 Consequences ("Full any-to-any with low latency","Crossbar grows quadratically with N; manageable at 4-16"), ADR-011 Decision (matches PR #87 / #91), and PLAN.md §2.2 frequency target"800 MHz – 1 GHz"— are all faithfully cited inline. The Open Questions list is appropriately scoped (scratchpad bundle shape pending Chipyard pin, routing-table entry count, back-pressure encoding, arbitration policy, zero-cycle bypass, concrete worst-case latency bound) — each lacks an ADR source and is honestly deferred rather than fabricated. The Stub's old "round-robin baseline" placeholder is explicitly downgraded to an open question rather than carried forward as a Draft commitment, which is the right call. Promotion history entry is appropriate.Findings
None.
CI green (head
de8190cc80), auto-approving