rtl(FluidPopSoC): chisel skeleton + chiseltest elaborate-only spec

navigator commented

2026-05-25 21:25:03 -03:00

Owner

Lands the §12.3 step 1 floor for the full-chip top: FluidPopSoC.scala
elaborates against Chipyard 1.13.0 pins with an IO bundle mirroring the
six bullets of SPEC §Interface (DDR5, PopLink quad-port, optional PCIe
Gen4 x16, JTAG/debug, clock+reset, BMC sideband). Every sub-bundle is
empty and tied to DontCare since SPEC §Interface is still TBD — no
widths, port counts or pin assignments are committed by this PR. The
spec file is untouched.

Acceptance criteria (issue #54)

rtl/src/pop/FluidPopSoC.scala exists, sbt compile green
IO bundle reflects SPEC §Interface (six sub-bundles, all DontCare, each with // TBD per SPEC §Interface annotations)
Top module — no parent wrapper exists yet on-die; child instantiation graph deferred to follow-up (MultiGemminiCluster / InterChipFabric / PopSoCConfig skeletons not yet present)
rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala exists; it should "elaborate" chiseltest harness; sbt Test/compile green
Source: SPDX-License-Identifier: CHARRUA-1.2; bench: SPDX-License-Identifier: AGPL-3.0-or-later
No fabricated widths/timing — every TBD field is DontCare with a // TBD per SPEC §<section> comment

Local validation

sbt compile        # green
sbt Test/compile   # green

Follow-ups (out of scope here): coverage targets and full behaviour
(PLAN.md §12.3 / §12.7), child instantiation graph once sibling
skeletons land, system bench (Verilator 1-chip / 2-chip / 8-chip
ladder per §8.3).

Closes #54

Lands the §12.3 step 1 floor for the full-chip top: FluidPopSoC.scala elaborates against Chipyard 1.13.0 pins with an IO bundle mirroring the six bullets of SPEC §Interface (DDR5, PopLink quad-port, optional PCIe Gen4 x16, JTAG/debug, clock+reset, BMC sideband). Every sub-bundle is empty and tied to `DontCare` since SPEC §Interface is still TBD — no widths, port counts or pin assignments are committed by this PR. The spec file is untouched. ## Acceptance criteria (issue #54) - [x] `rtl/src/pop/FluidPopSoC.scala` exists, `sbt compile` green - [x] IO bundle reflects SPEC §Interface (six sub-bundles, all `DontCare`, each with `// TBD per SPEC §Interface` annotations) - [x] Top module — no parent wrapper exists yet on-die; child instantiation graph deferred to follow-up (MultiGemminiCluster / InterChipFabric / PopSoCConfig skeletons not yet present) - [x] `rtl/tests/FluidPopSoC/FluidPopSoCSpec.scala` exists; `it should "elaborate"` chiseltest harness; `sbt Test/compile` green - [x] Source: `SPDX-License-Identifier: CHARRUA-1.2`; bench: `SPDX-License-Identifier: AGPL-3.0-or-later` - [x] No fabricated widths/timing — every TBD field is `DontCare` with a `// TBD per SPEC §<section>` comment ## Local validation ``` sbt compile # green sbt Test/compile # green ``` Follow-ups (out of scope here): coverage targets and full behaviour (PLAN.md §12.3 / §12.7), child instantiation graph once sibling skeletons land, system bench (Verilator 1-chip / 2-chip / 8-chip ladder per §8.3). Closes #54

navigator added 1 commit

2026-05-25 21:25:03 -03:00

rtl(FluidPopSoC): chisel skeleton + chiseltest elaborate-only spec

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3c25365646

Lands the §12.3 step 1 floor for the full-chip top: FluidPopSoC.scala
elaborates against Chipyard 1.13.0 pins with an IO bundle mirroring the
six bullets of SPEC §Interface (DDR5, PopLink quad-port, optional PCIe,
JTAG/debug, clock+reset, BMC sideband). Every sub-bundle is empty and
tied to DontCare since the SPEC §Interface section is still TBD — no
widths, port counts or pin assignments are committed by this PR.

FluidPopSoC.scala carries CHARRUA-1.2; FluidPopSoCSpec.scala carries
AGPL-3.0-or-later. The spec file is untouched.

Why: the per-module verification floor in PLAN.md §12.3 requires every
module to elaborate before any behaviour, golden model or coverage work
begins. Until MultiGemminiCluster / InterChipFabric / PopSoCConfig
skeletons land, this top stands alone — the full child instantiation
graph arrives in a follow-up once those sibling skeletons exist.

navigator added the

ready-for-review

label

2026-05-25 21:25:10 -03:00

navigator commented

2026-05-25 21:27:28 -03:00

Author

Owner

VERDICT: PASS

PR #83 adds the §12.3 step-1 floor for FluidPopSoC — full-chip top module + chiseltest harness — and is mechanically clean throughout. SPDX headers are correct (CHARRUA-1.2 for the RTL source, AGPL-3.0-or-later for the test), both files declare package pop matching the canonical package, and the IO bundle mirrors the six bullets of SPEC §Interface exactly — ddr5, popLink, pcie, jtagDebug, clockReset, bmc — each as an empty sub-bundle tied to DontCare with // TBD per SPEC §Interface annotations. No widths, port counts, or pin assignments are committed; the chiseltest bench has the prescribed it should "elaborate" floor. Every numerical claim in the source comments traces back to either the SPEC or a cited ADR: "50 W typ / 70 W max per chip (ADR-012)" and "~1100-ball BGA pin budget (ADR-014)" come straight from SPEC §Invariants, "two Rocket cores (ADR-006)", "one DDR5 controller (ADR-005)", "designated-master variant (ADR-008)", and "2D-torus quad-port (ADR-010)" mirror the SPEC body and ADR citations. The optional-PCIe deferral and child-instantiation deferral are both honest: OptionalPcieIO is empty pending PCIeHostBridge.SPEC.md, and the child instantiation graph is explicitly held off until MultiGemminiCluster / InterChipFabric / PopSoCConfig skeletons are landed. Scope matches Issue #54 (two new files, no drive-by edits), no AI/Anthropic attribution, no off-limits paths, no fabricated VC counts or topology numbers like the issues flagged on PR #81 and PR #82.

Findings

None.

**VERDICT:** PASS PR #83 adds the §12.3 step-1 floor for `FluidPopSoC` — full-chip top module + chiseltest harness — and is mechanically clean throughout. SPDX headers are correct (`CHARRUA-1.2` for the RTL source, `AGPL-3.0-or-later` for the test), both files declare `package pop` matching the canonical package, and the IO bundle mirrors the six bullets of SPEC §Interface exactly — `ddr5`, `popLink`, `pcie`, `jtagDebug`, `clockReset`, `bmc` — each as an empty sub-bundle tied to `DontCare` with `// TBD per SPEC §Interface` annotations. No widths, port counts, or pin assignments are committed; the chiseltest bench has the prescribed `it should "elaborate"` floor. Every numerical claim in the source comments traces back to either the SPEC or a cited ADR: "50 W typ / 70 W max per chip (ADR-012)" and "~1100-ball BGA pin budget (ADR-014)" come straight from SPEC §Invariants, "two Rocket cores (ADR-006)", "one DDR5 controller (ADR-005)", "designated-master variant (ADR-008)", and "2D-torus quad-port (ADR-010)" mirror the SPEC body and ADR citations. The optional-PCIe deferral and child-instantiation deferral are both honest: `OptionalPcieIO` is empty pending `PCIeHostBridge.SPEC.md`, and the child instantiation graph is explicitly held off until `MultiGemminiCluster` / `InterChipFabric` / `PopSoCConfig` skeletons are landed. Scope matches Issue #54 (two new files, no drive-by edits), no AI/Anthropic attribution, no off-limits paths, no fabricated VC counts or topology numbers like the issues flagged on PR #81 and PR #82. ## Findings _None._

navigator added the

review:pass

label

2026-05-25 21:27:28 -03:00